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PCM5122: Hardwire mode: How to configure register 20-24 to get a properly PllCK?

Part Number: PCM5122

Hi team

    How to configure register 20-24 to get a properly PllCK? customer meet a problem when use hardwired mode. there is no sound When there is no SCK signal, After adding the SCK, there is sound.  All hardware circuits are correct。 I thought it‘s because K*R/P don't get a right configuration.

     

  • There are 2 folds to this issue, SCLK and  the correct register set up as you mentioned yourself:

    1- The PCM512x requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. However the system clock PLL mode allows designers to use a simple 3-wire I 2S audio source. In hardwired mode, the internal PLL is disabled as soon as an external SCK is supplied. In hardwired mode, the device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock.

    2- Having said that, care must be taken when the ratios are being  calculated and set . Here is  a general guideline for this part:

    Table 133 is the recommended clock divider settings for PLL as Master Clock (in VCOM Mode). please use the values in this table to configure the registers listed in Table 34. (PLL Configuration Registers)

     Please also note the mapping in table 133 and table 34 (for example MDAC in table 133 is the value of DDSP in table 34, NDAC is the value of  DACCK, NCP is the value of CPCK and DOSR is the value of OSRCK.)  Please also note for correct operation DOSR must be chosen such that MOD fS / DOSR = 16 ( Refer to Table 36). The PLL coefficient  itself (from table 133)  can be written to PLL registers in table 35.

    Regards,

    Arash