Hello,
I'm trying to understand how to set the BCK clock input rate when using the ADC in PCM mode, Left-Justified data format, Slave Mode, Normal speed mode
quoting the datasheet (pag. 21):
For the I2S and Left-Justified data formats, the BCK clock output rate is fixed in Master mode, with the Normal
mode being 128fS and the Double and Quad Speed modes being 64fS. In Slave Mode, a BCK clock input rate of
64fS or 128fS is recommended for Normal mode, while 64fS is recommended for Double and Quad Rate modes.
My master device that will generate the clocks for the PCM4222 will provide a BCK clock of 64fS (along with LRCK of 1fS and MCK of 256fS).
Would the PCM4222 automatically detect that the BCK is 64fS and not 128fS? otherwise I don't understand how that setting should be made on the PCM4222.
