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PCM6340-Q1: Clock frequency issue

Zirui Su
Expert 5340 points
Part Number: PCM6340-Q1

Hi team

I would like to ask a question about PCM6340 clock frequency.

Customer expects to use the internal clock of the device, PIN28 GPIO1 has np MCLK input; but after the configuration is completed, the frequency of PIN31 FSYNC customer measured is different from the configured frequency; modify the register configuration according to the datasheet, the output frequency is still different from the value on the datasheet.

Here is their configuration both hardware part and software part:

Schematic:

Initial register configuration:

PCM6340 init .xlsx
Test Results:
1. Address0x14: If FS_RATE is configured as 48kHz, the actual measurement is 14.7kHz; if configured as 16kHz, the actual measurement is 4.86 kHz.
2. Connect a 12.288MHz crystal oscillator to GPIO1, the actual measured PIN31 FSYNC frequency is the same as the configured frequency.

Could you please help analyze whether there is a problem with our design and how to modify it to accurately output the clock? Thank you.

  • 0
    TI__Genius 13610 points

    Hello Zirui,

    If you are using device in master mode as you have set currently in the register configuration a MCLK clock must be inputted to device for it to function. MCLK is only optional in slave configuration.

    Best Regards,

    Carson

    Low Power Audio Applications Engineer

  • 0 in reply to Carson Allen
    TI__Expert 5340 points

    HI Carson,

    I would like to know the following application scenario is feasible:

    1. No MCLK input for PCM6340Q1
    2. Customer would like to use internal PLL
    3. PCM6340 as the main output Audio CLK (Sample rate: 48khz)
    4. Two-channel IIS outputs

    How to understand the MST_CFG0 description:

    When PCM6340 is configured as Master mode, it still needs external MCLK source input right? If there is no external MCLK input, can PCM6340 output Audio clk normally or this must be in PCM6340 slave mode?

    I check their register value, they configured the PCM6340 in master mode and PLL is enable, do you mean we still need a MCLK external source input to the PCM6340? We just want to use the internal clock and do not want to use external MCLK source, thank you.

  • 0 in reply to Zirui Su
    TI__Genius 13610 points

    Yes if you want to use device as master and act as a clock source for BCK and FSYNC then a MCK must be inputted. The PLL is implemented as a regulator to generate proper clocking for audio protocol, it cannot naturally generate super high frequencies to act as a master clock, hence the point of the last two bits in the  Only in slave mode is no MCLK required.

    Best Regards,

    Carson