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TPA3255: question on TPA3255

Qiannan Wang
Prodigy 25 points
Part Number: TPA3255

hi audio team,

I have few questions about TPA3255.

Q1: The experiment config is PBTL mode with 2ohm pure resistance loading. Using external clk (2M) and PVDD is set to 32V;

when checking the switching performance, the input signal frequency(sent out from AP) is 30Hz, Fault _L signal will be triggered when input voltage is at range 1.27V-1.45V. except the below range, tpa3255 can work normally. Pretty weird.

But there's two way to solving this issue while I cannot explain the reason. first is to increase PVDD voltage. then under same condition, fault l won't be triggered to LOW.

second way is to increase the OSC clk(to around 2.7M), fault_l will not be triggered to low.

can you help to explain why these two solutions have here? especially is there any requirement on external clk value selection?

Q2:

when clipping protection is triggered. narrow wide pulse can be found and sw-p and sw-n have lots of overlap here.

is it normal??

  • 0
    TI__Genius 9140 points

    Hello Qiannan,

    I am looking into this, will feedback you today.

    Dylan

  • 0
    TI__Genius 9140 points

    Qiannan,

    Q1:  from the OTW pin, i guess you already find some hints. I suspect the fault_L is caused by this OTW->OTE, as the OTE is continously reported at high output power, but not happens at peak current point, which ruled out OC fault.

    To explain the reason of effective two actions (1)increase PVDD will avoid CBC trigged, that will decrease thermal dissipation (2)higher Osc result in lower ripple current, not able to trigger CBC. 

    Q2: That should be the CBC limit. when it reaches CBC current limit, then an addtional pulse is inserted to reduce current output.

    Dylan

  • 0 in reply to Dylan Yao
    Prodigy 25 points

    Hi Dylan,

    What is CBC? is it the CB3C mentioned in datasheet? While we're using latch OC mode instead of CB3C mode. is there any difference?

    I try to change the OC_ADJ Resistor Value from 64K to 50K(still latch oc mode but with higher oc current), shutdown still exists here. Technically if this is triggered by CBC, do you think changing OC_ADJ Resistor value will solve this issue?  And also, the datasheet gives instruction on OSC's typical value selection is 2.7M, is there any concern if I use 2M clk?

    The second weird thing is that if I keep increase the input voltage to around 1.5v, amp will work normally, which do not seems like thermal triggered.

  • 0 in reply to Qiannan Wang
    TI__Genius 9140 points

    Qiannan,

    Yes, it is the CB3C mentioned in datasheet. CBC function is default available, it is different from OC.

    As last post, i suspect this is OT fault, instead of OC. you can go check the current waveform to confirm that.

    the behavior of "keep increase the input voltage to around 1.5v, amp will work normally," was explained in last post Q2.

    the possible solution would be: (1)limit the power. (2)improve system thermal design

      

    Dylan