TLV320ADC5140: [TLV320ADCX140] About the clk timing problem

Hello,

Could I see your register settings and clarify what color corresponds to what on that screenshot?

Best Regards,

Carson

Hi,Carson Allen

Sorry for late repply,our holiday has just ended.

This is register map:

And about the picture,pink is BCLK,adn green is data clk.

thanks

Hello,

Thanks for this info, I will take a look and respond by early next week.

Best Regards,

Carson

Hi,Carson Allen

Any suggestions?

Hardware team asked to solve the problem.

thanks

Hello,

Based on the shape of the data line it seems like the core problem is there is a pretty high capacitive load on the data line., Are these measurements off a PCB at a test point or at pin of device? There could be some phase shifting going on here.

Also could you perform test with slower rate to see if problem still occurs as you see in this case

Best Regards,

Carson

Hi,

There is the nearest and farthest signal from the chip.

There doesn't seem to be much deviation.

Please help check it.

thanks

Hello,

To understand more, BCLK is set to trigger at falling edge right? and where WCLK fit into all of this? Are there other components on board on dataline?

A schematic might help

Best Regards,

Carson

Hi,

There is register map:

From the register info,BCLK shou default rising edge effective.

And we use four ADC IC for 32 slot.

TDM RX is tas5805.

thanks

Hello,

If you have it triggering on rising edge than why is your time measurement relative to the falling edge of BCLK?

Best,

Carson

Hi,

Yes,hardware team tested falling edge.

For register 0x07,the BCLK and DATA polarity is reg 0 which is default polarity.

So that's mean default polarity is rising edge?

thanks