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TLV320ADC3120: Not output from SDOUT

Part Number: TLV320ADC3120

Hi Expert, 

My customer have an issue that is not output from SDOUT with smaller value of BCLK/FSYNC Ratio than 64.

Could you please give me your advice?

Customer want to set MCLK=14.7456MHz, FSYNC_OUT384kHz and BCLK= 12.288MHz(/or 9.216MHz).

OK setting (but, it is not the configuration customer want)

MCLK=14.7456MHz

BCLK Div Value3

FSYNC Div Value64

PLL J-Multi5

PLL D-Multi0

Calculated output

BCLK_OUT=24.576MHz

FSYNC_OUT384.0000kHz

BCLK/FSYNC Ratio=64

NG setting#1

BCLK Div Value:6

FSYNC Div Value:32

Calculated output

BCLK_OUT=12.2880MHz

FSYNC_OUT384.0000kHz

BCLK/FSYNC Ratio=32

*SDOUT was not output

NG setting#2

BCLK Div Value:8

FSYNC Div Value24

Calculated output

BCLK_OUT=9.2160MHz

FSYNC_OUT384.0000kHz

BCLK/FSYNC Ratio=24

*SDOUT was not output

Thanks

Muk