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PCM1681: Customer wants to combined use LRCK for DSD compatible model

Part Number: PCM1681
Other Parts Discussed in Thread: PCM9211, PCM1862,

Hello expert,

This is Koki Tsushima.

I want to ask about PCM1681 can be used LRCK for DSD compatible model.

Customer wants to common I2S between this PCM1681 and other DAC.

When the situation above on DSD, are there no issues to input the DSD data to PCM1681?

For that time, LRCK will be DSD and DSD can be 2.8M to 11.2MHz.

I know PCM1681 is not for DSD DAC, but I want to ask it is possible to combined use LRCK.

Best regards,

Koki Tsushima

  • Hello Sir,

    As  you noted PCM1681 doesn't support DSD (other DAC such as PCM9211 support) so if your question is to send the I2S that you sent to PCM1681  to another DAC as DSD, I can not comment on that. Also you mentioned LRCK ( sampling frequency)  will be DSD of 2.8M to 11.2MHz for another DAC but seems you are talking about SCK or BCLK not LRCK. 

    At any rate,  PCM1681 doesn't support DSD. 

    Kind Regards,

    arash

  • Hello Arash-san,

    Thank you for your reply. 

    I understood that you cannot comment for my answer, therefore, I fix my questions as follows.

    "What will be expected to PCM1862 when the unexpected DSD Data signal was inserted to LRCK?"

     - Will the PCM1862 be broken electrically?

     - Will the PCM1862 be malfunctioned, but will not be broken?

    - Or will any other cases be expected? 

    I personally think if it is for second case, customer can common that signal.

    But for the first case, he has to be independent the signal lines.

    Best regards,

    Koki Tsushima

  • Hello Koki-san,

    If an unexpected DSD data signal is sent to LRCK, no damage will be resulted, because as far as the pin is concerned, just  a "wrong" signal  is sent to it and  therefore the part  should not function. Maximum Input voltage to digital pins for PCM1681 is 6.5V.

    Kind Regards,

    Arash

  • Hi Arash-san,

    It is good to know that the device will not be broken.

    How about the behavior when that data put into LRCK?

    ・No output varies at all?

    ・Pop noise will be occurred due to the quick varies?

      i.e. DSD data was input just after the PCM data

    ・Cannot expected?

    If it is difficult to expect, but are there any good methods to prevent the bad effect for Audio?

    I assume that if soft-mute (or hard-mute?) is activated, there are no effects for sound even though the output was varied due to DSD data.

    Is this understanding correct?

     

  • Hello Koki-san,

    I have never done this experiment with DSD on non-DSD part so I can not give you a definite answer except that  once the device is muted,  there should be no pop noise.

    I think the best way is for them to   try and see how it works out for them in their specific set up.

    Regards,

    Arash

  • Hello Arash-san,

    I understood you could not give me a definite answer.

    But how about "hung"?

    Is this device(s) will have possibility to 'hung' or system halt?

    Regards,

    Koki

  • Hello Koki-san,

    I would think using it in this configuration , there is possibility for system halt or hung . Having said that, i would think only this DAC would not work (non-DSD) and the other DAC (DSD)  should be okay. So may be the whole system would not halt but would not work as intended either.

    Regards,

    Arash

  • Hi Arash-san,

    I want to ask about the possibility for system halt or hung.

    Is this mean that customer has to power-off once in order to get buck normal operation?

    Or will it recover without power supply is not changed ? If so, do you have any ideas when PCM1681 will re-activate?

    Best regards,

    Koki Tsushima

  • Hello Koki-san, Unfortunately I can not give you an answer for that as we have never used it this way. But if I have to guess, I would think a power off would be needed to get back to normal operation. 

    Regards,

    Arash

  • Hi Arash-san,

    Was it the case you though as a worst case?

    Or can be done by design issue?

    On 8.3.3, it is written as follows.

    Internal operation of the PCM1681 and PCM1681-Q1 is synchronized with LRCK. Accordingly, internal operation
    is suspended when LRCK is changed or when SCK and/or BCK is interrupted for at least 3-bit clock cycles. If
    SCK, BCK, and LRCK are provided continuously after this held condition, the internal operation is
    resynchronized automatically within the following 3/fS period. External resetting is not required.

    So I think this should be the worst case.

    BR

    Koki 

  • Hello Koki-san,

    Yes, this is the worst case scenario, but I would think this would happen in all likelihood. 

    Regards,

    Arash