Hi Ti team,
We are now trying to make LINE1L output to Lout directly while recording and here is the input/output signal spec for our application:
1. Line1L: 5~750 mVrms
2. LEFT_LOP/LEFT_LOM: 250~750 mVrms
The problems we facing are:
1. Could we output the Line1L signal to left out through "PGA_L" by open register 81? What's else should be setup at the same time?

2. From the input spec provided, if we hope to maintain and limit the output voltage at 750 mVrms with all input voltage (5~750 mVrms), is it possible by setting AGC function to fulfill that?
Please help to check the questions above, thanks.
BRs,
Jerry
