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TPA3251: Voltage offset and Pop noise

Part Number: TPA3251

Hi Experts,

Good day.

Client's tested ICs have offsets between 0 and 30mV. All of them satisfy the Pop noises on Power up and Power down. They're planning to use the TPA3251, and have the following queries:

  1. Is the analyzed relation of Output offset voltage and Pop noise correct?
  2. Can we expect ICs with Output offset voltages of 30 to 60mV to still meet our limits?
  3. What is the statistical chance of getting a IC with output offset voltage > 30mV?

Thank you for your support.

Regards,
Archie A.

  • ArTzy,

    Is the analyzed relation of Output offset voltage and Pop noise correct?

    Yes, there is strong relation of output offset voltage and pop noise. pop noise happens due to OUTP-OUTN differential voltage when they ramp up to different level(offset).  the higher offset, the larger pop noise.

    Can we expect ICs with Output offset voltages of 30 to 60mV to still meet our limits?

    It depends on how much increment of pop noise and how is your limits. The best practical way is still test that.

    What is the statistical chance of getting a IC with output offset voltage > 30mV?

    It depends on our fab process distribution. Datasheet specified max is 60mV, so there is definitely chance to be 60mV for one unit.  So we still suggest you find one device with large offset and test the impact to pop noise.