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PCM1794A: Differential output in digital filter bypass mode

wang tianqi
Prodigy 20 points
Part Number: PCM1794A
Other Parts Discussed in Thread: NE5534, PCM1794

Hi,TI !

I used the external filter mode for digital-to-analog conversion,and I used  the IOUTL differential pair outputs in the circuit diagram using the NE5534 in the datasheet.

Are  the following Settings appropriate for PCM1794?

Settings:

BCK  25Mhz

DATA   24-bit

WDCK  1Mhz

SCK   24Mhz or 50Mhz

I  used these Settings because I need to  feed DATA into PCM1794 in a us.  When I used these Settings ,the output of NE5534 is always -5.8V.  No matter what the DATA  is, the output is always -6.3V.

Thanks for any help in this.

tq

  • 0
    TI__Mastermind 19360 points

    Hello, can you clarify what is your WDCK, we have sampling frq (Fs or LRCK )

    You  can use this simple equation to figure out if a given BCLK works  for you or not.

     BLK= word length(bit) x number of channels x Fs x number of devices.

    Usually SCK is a multiple of Fs such as 256Fs, 128Fs or ....

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 20 points

    Hi, .

    I just want to use PCM1794 for digital to analog conversion. I don't know the sampling frq ( Fs ).

    My DATA  is  24-bit ,and BCK is 25MHz .The data transfer period is 1 us, so the WDCK is 1MHz. 

    I used PCM1794 in digital filter bypass mode, so the  WDCK is LRCK.  In this case, Are  the following Settings appropriate for PCM1794?

    Settings: BCK 24Mhz or 50MHz . If not, please tell me what Settings are appropriate for the PCM1794.

    Apart from that, I have another question. No matter what the DATA  is, the output of NE5534 is always -6.3V. Does this mean that the PCM1794

    has been reset and has not started running yet?

    Thanks for any help in this.

    tq

  • 0 in reply to wang tianqi
    TI__Mastermind 19360 points

    Hello, PCM1794 and most of our  audio DACs have a max fs of 200KHz . From its

    datasheet you see 

    Sampling Frequency: 10 kHz to 200 kHz.   BCK pulse-cycle time=20n ==> the Max BCK rate of this part is about 50MHz,

    from this you can have a BCLK of 50MHz or 25MHz , but your 1MHz sampling freq is not compatible with this part. 

    Please  also refer to Table 2. System Clock Rates for Common Audio Sampling Frequencies for possible Fs and Sys clk.

    Once you fix this , we can move on to the next issue but I don't think the chip will work with this setup.

    Regards,

    Arash

  • 0 in reply to Arash Loloee
    Prodigy 20 points

    Hi, .

    Thanks for your reply.

    Please tell me is it necessary for SCK to use the frequency recommended in the Table 2. If my fs is not in the Table 2  for example fs is 125khz,

    can I use 128fs or 192fs as my SCK? 

    Or when SCK is 49.152MHz in Table 2, can I use 50MHz instead of  49.152MHz?

    When I used PCM1794 in digital filter bypass mode, WDCK is 8X fs. My WDCK is 1Mhz. Does it mean that my fs is 125khz ? 

    Thanks for any help in this.

    tq

  • +1 in reply to wang tianqi
    TI__Mastermind 19360 points

    Hello,  Please note this is audio dac and its sampling frequencies between the acceptable range of <200KHz  are listed in table 2. 

    I2S protocol for audio DACs requires  sampling frequencies such as  44.1K, 48k,96,192K  and then the exact multipliers as mentioned in the table  for the given sampling freq to obtain BCLK and SCLK. 

    it seems your data is not Audio data, I think you should  use a non audio dac.

    Regards,

    Arash