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TLV320AIC3100: TLV320AIC31XX Linux driver issue - sound: parse error -22

Part Number: TLV320AIC3100

Hi,

I am currently bringing up a device with an TLV320AIC3100 TI codec assembled, but I getting following error during driver initialization:

[    4.104750] asoc-audio-graph-card sound: parse error -22
[    4.108728] asoc-audio-graph-card: probe of sound failed with error -22

I am using Linux kernel version 5.4 , PHYTEC STM32MP1 SoM is used.

This is the relevant device tree part:

#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
/ {
	 sound {
	 		compatible = "audio-graph-card";
	 		label = "STM32MP1-PHYCORE";
	 		routing = "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */
	 		"Capture", "MCLK";
	 		dais = <&sai2b_port &sai2a_port>;
	 		status = "okay";
	 };
};

&i2c1 {
	codec: tlv320@18 {
		compatible = "ti,tlv320aic3100";
		#sound-dai-cells = <0>;
		reg = <0x18>;
		status = "okay";
		ai31xx-micbias-vg = <2>;
		/* gpio-reset = <&gpio5 8 GPIO_ACTIVE_LOW>; */
		ai31xx-ocmv = <2>;


		HPVDD-supply = <&v3v3>;
		SPRVDD-supply = <&v3v3>;
		SPLVDD-supply = <&v3v3>;
		AVDD-supply = <&v3v3>;
		IOVDD-supply = <&v3v3>;
		DVDD-supply = <&v1v8_audio>;
		clocks = <&sai2b>;
		clock-names = "MCLK";

		tlv320_port: port {
			#address-cells = <1>;
			#size-cells = <0>;
			tlv320_tx_endpoint: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&sai2b_endpoint>;
				frame-master;
				bitclock-master;
			};

			tlv320_rx_endpoint: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&sai2a_endpoint>;
				frame-master;
				bitclock-master;
			};
		};
	};
};


&sai2 {
	clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
	clock-names = "pclk", "x8k", "x11k";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_a>;
	pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_a>;
	status = "okay";

	sai2a: audio-controller@4400b004 {
		compatible = "st,stm32-sai-sub-a";
		dma-names = "rx";
		st,sync = <&sai2b 2>;
		status = "okay";
		clocks = <&rcc SAI2_K>, <&sai2b>;
		clock-names = "sai_ck", "MCLK";

		sai2a_port: port {
			sai2a_endpoint: endpoint {
				remote-endpoint = <&tlv320_rx_endpoint>;
				format = "i2s";
				mclk-fs = <256>;
				dai-tdm-slot-num = <2>;
				dai-tdm-slot-width = <16>;
			};
		};
	};

	sai2b: audio-controller@4400b024 {
		compatible = "st,stm32-sai-sub-b";
				#clock-cells = <0>;
				dma-names = "tx";
				clocks = <&rcc SAI2_K>;
				clock-names = "sai_ck";
				status = "okay";

				sai2b_port: port {
						sai2b_endpoint: endpoint {
								remote-endpoint = <&tlv320_tx_endpoint>;
								format = "i2s";
								mclk-fs = <256>;
								dai-tdm-slot-num = <2>;
								dai-tdm-slot-width = <16>;
						};
				};
		};
};

This is the i2c register dump 

root@phycore-stm32mp1-3:/boot# i2cdump  -y 0 0x18
No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 00 01 66 00 11 04 00 00 00 00 01 01 00 80 80    ..?f.??....??.??
10: 08 00 01 01 80 80 04 00 00 00 01 00 00 00 01 00    ?.?????...?...?.
20: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00    ....?...........
30: 00 00 00 02 32 12 03 02 02 11 10 00 01 04 00 14    ...?2??????.??.?
40: 0c 00 00 00 6f 38 00 00 00 00 00 ee 10 d8 7e e3    ?...o8.....???~?
50: 00 00 80 00 00 00 00 00 7f 00 00 00 00 00 00 00    ..?.....?.......
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
root@phycore-stm32mp1-3:/boot#

Maybe someone can help me solve this issue

  • Hi,

    I'll ask our Linux expert to assist with the Linux error.

    From register you are configuring the codec as slave in I2S 16 bit format and both DAC and ADC are powered down.

    So basically nothing is enabled in codec.

    Regards,

    Peter

  • The driver didn't supported my "MCLK" so routing failed. My MCLK 12.8MHz was also not supported by the aic31x clock divs. I also integrated all fixed from upstream linux kernel master.  Audio Output is now working, microphone currently not.  I am playing around with alsamixer settings but so far I didn't get the microphone working. Will update my answer If I get it running. 

    diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c
    index df627a08d..6916e310d 100644
    --- a/sound/soc/codecs/tlv320aic31xx.c
    +++ b/sound/soc/codecs/tlv320aic31xx.c
    @@ -2,7 +2,7 @@
     /*
      * ALSA SoC TLV320AIC31xx CODEC Driver
      *
    - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
    + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
      *	Jyri Sarha <jsarha@ti.com>
      *
      * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
    @@ -12,6 +12,7 @@
      * and mono/stereo Class-D speaker driver.
      */
     
    +#include <linux/clk.h>
     #include <linux/module.h>
     #include <linux/moduleparam.h>
     #include <linux/init.h>
    @@ -35,6 +36,9 @@
     
     #include "tlv320aic31xx.h"
     
    +static int aic31xx_set_jack(struct snd_soc_component *component,
    +                            struct snd_soc_jack *jack, void *data);
    +
     static const struct reg_default aic31xx_reg_defaults[] = {
     	{ AIC31XX_CLKMUX, 0x00 },
     	{ AIC31XX_PLLPR, 0x11 },
    @@ -165,17 +169,21 @@ struct aic31xx_priv {
     	struct aic31xx_pdata pdata;
     	struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
     	struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
    +	u32 sysclk_id;
     	struct snd_soc_jack *jack;
     	unsigned int sysclk;
    +	struct clk *mclk_handle;
     	u8 p_div;
     	int rate_div_line;
     	bool master_dapm_route_applied;
     	int irq;
    +	u8 ocmv; /* output common-mode voltage */
     };
     
     struct aic31xx_rate_divs {
     	u32 mclk_p;
     	u32 rate;
    +	u8 pll_r;
     	u8 pll_j;
     	u16 pll_d;
     	u16 dosr;
    @@ -188,51 +196,82 @@ struct aic31xx_rate_divs {
     
     /* ADC dividers can be disabled by configuring them to 0 */
     static const struct aic31xx_rate_divs aic31xx_divs[] = {
    -	/* mclk/p    rate  pll: j     d        dosr ndac mdac  aors nadc madc */
    +	/* mclk/p    rate  pll: r  j     d     dosr ndac mdac  aors nadc madc */
     	/* 8k rate */
    -	{12000000,   8000,	8, 1920,	128,  48,  2,	128,  48,  2},
    -	{12000000,   8000,	8, 1920,	128,  32,  3,	128,  32,  3},
    -	{12500000,   8000,	7, 8643,	128,  48,  2,	128,  48,  2},
    +	{  512000,   8000,	4, 48,    0,	128,  48,  2,   128,  48,  2},
    +	{12000000,   8000,	1,  8, 1920,	128,  48,  2,	128,  48,  2},
    +	{12000000,   8000,	1,  8, 1920,	128,  32,  3,	128,  32,  3},
    +	{12288000,   8000,	1,	8,    0,	128,  48,  2,	128,  48,  2},
    +	{12500000,   8000,	1,  7, 8643,	128,  48,  2,	128,  48,  2},
     	/* 11.025k rate */
    -	{12000000,  11025,	7, 5264,	128,  32,  2,	128,  32,  2},
    -	{12000000,  11025,	8, 4672,	128,  24,  3,	128,  24,  3},
    -	{12500000,  11025,	7, 2253,	128,  32,  2,	128,  32,  2},
    +	{  705600,  11025,	3, 48,    0,	128,  24,  3,	128,  24,  3},
    +	{12000000,  11025,	1,  7, 5264,	128,  32,  2,	128,  32,  2},
    +	{12000000,  11025,	1,  8, 4672,	128,  24,  3,	128,  24,  3},
    +	{12288000,  11025,	1,  7, 3500,	128,  32,  2,	128,  32,  2},
    +	{12500000,  11025,	1,  7, 2253,	128,  32,  2,	128,  32,  2},
     	/* 16k rate */
    -	{12000000,  16000,	8, 1920,	128,  24,  2,	128,  24,  2},
    -	{12000000,  16000,	8, 1920,	128,  16,  3,	128,  16,  3},
    -	{12500000,  16000,	7, 8643,	128,  24,  2,	128,  24,  2},
    +	{  512000,  16000,	4, 48,    0,	128,  16,  3,	128,  16,  3},
    +	{ 1024000,  16000,	2, 48,    0,	128,  16,  3,	128,  16,  3},
    +	{12000000,  16000,	1,  8, 1920,	128,  24,  2,	128,  24,  2},
    +	{12000000,  16000,	1,  8, 1920,	128,  16,  3,	128,  16,  3},
    +	{12288000,  16000,	1,  8,    0,	128,  24,  2,	128,  24,  2},
    +	{12500000,  16000,	1,  7, 8643,	128,  24,  2,	128,  24,  2},
     	/* 22.05k rate */
    -	{12000000,  22050,	7, 5264,	128,  16,  2,	128,  16,  2},
    -	{12000000,  22050,	8, 4672,	128,  12,  3,	128,  12,  3},
    -	{12500000,  22050,	7, 2253,	128,  16,  2,	128,  16,  2},
    +	{  705600,  22050,	4, 36,    0,	128,  12,  3,	128,  12,  3},
    +	{ 1411200,  22050,	2, 36,    0,	128,  12,  3,	128,  12,  3},
    +	{12000000,  22050,	1,  7, 5264,	128,  16,  2,	128,  16,  2},
    +	{12000000,  22050,	1,  8, 4672,	128,  12,  3,	128,  12,  3},
    +	{12288000,  22050,	1,  7, 3500,	128,  16,  2,	128,  16,  2},
    +	{12500000,  22050,	1,  7, 2253,	128,  16,  2,	128,  16,  2},
     	/* 32k rate */
    -	{12000000,  32000,	8, 1920,	128,  12,  2,	128,  12,  2},
    -	{12000000,  32000,	8, 1920,	128,   8,  3,	128,   8,  3},
    -	{12500000,  32000,	7, 8643,	128,  12,  2,	128,  12,  2},
    +	{ 1024000,  32000,	2, 48,   0,		128,  12,  2,	128,  12,  2},
    +	{ 2048000,  32000,	1, 48,   0,		128,  12,  2,	128,  12,  2},
    +	{12000000,  32000,	1,	8, 1920,	128,  12,  2,	128,  12,  2},
    +	{12000000,  32000,	1,	8, 1920,	128,   8,  3,	128,   8,  3},
    +	{12288000,  32000,	1,  8,    0,	128,  12,  2,	128,  12,  2},
    +	{12500000,  32000,	1,	7, 8643,	128,  12,  2,	128,  12,  2},
     	/* 44.1k rate */
    -	{12000000,  44100,	7, 5264,	128,   8,  2,	128,   8,  2},
    -	{12000000,  44100,	8, 4672,	128,   6,  3,	128,   6,  3},
    -	{12500000,  44100,	7, 2253,	128,   8,  2,	128,   8,  2},
    +	{ 1411200,  44100,	2, 32,    0,	128,   8,  2,	128,   8,  2},
    +	{ 2822400,  44100,	1, 32,    0,	128,   8,  2,	128,   8,  2},
    +	{12000000,  44100,	1,  7, 5264,	128,   8,  2,	128,   8,  2},
    +	{12000000,  44100,	1,  8, 4672,	128,   6,  3,	128,   6,  3},
    +	{12288000,  44100,	1,	7, 3500,	128,   8,  2,	128,   8,  2},
    +	{12500000,  44100,	1,  7, 2253,	128,   8,  2,	128,   8,  2},
     	/* 48k rate */
    -	{12000000,  48000,	8, 1920,	128,   8,  2,	128,   8,  2},
    -	{12000000,  48000,	7, 6800,	 96,   5,  4,	 96,   5,  4},
    -	{12500000,  48000,	7, 8643,	128,   8,  2,	128,   8,  2},
    +	{ 1536000,  48000,	2, 32,   0,		128,   8,  2,	128,   8,  2},
    +	{ 3072000,  48000,	1, 32,   0,		128,   8,  2,	128,   8,  2},
    +	{12000000,  48000,	1,  8, 1920,	128,   8,  2,	128,   8,  2},
    +	{12000000,  48000,	1,  7, 6800,	 96,   5,  4,	 96,   5,  4},
    +	{12288000,  48000,	1,	8,    0,	128,   8,  2,	128,   8,  2},
    +	{12500000,  48000,	1,  7, 8643,	128,   8,  2,	128,   8,  2},
     	/* 88.2k rate */
    -	{12000000,  88200,	7, 5264,	 64,   8,  2,	 64,   8,  2},
    -	{12000000,  88200,	8, 4672,	 64,   6,  3,	 64,   6,  3},
    -	{12500000,  88200,	7, 2253,	 64,   8,  2,	 64,   8,  2},
    +	{ 2822400,  88200,	2, 16,   0,	 64,   8,  2,	 64,   8,  2},
    +	{ 5644800,  88200,	1, 16,   0,	 64,   8,  2,	 64,   8,  2},
    +	{12000000,  88200,	1, 7, 5264,	 64,   8,  2,	 64,   8,  2},
    +	{12000000,  88200,	1, 8, 4672,	 64,   6,  3,	 64,   6,  3},
    +	{12288000,  88200,	1, 7, 3500,	 64,   8,  2,	 64,   8,  2},
    +	{12500000,  88200,	1, 7, 2253,	 64,   8,  2,	 64,   8,  2},
     	/* 96k rate */
    -	{12000000,  96000,	8, 1920,	 64,   8,  2,	 64,   8,  2},
    -	{12000000,  96000,	7, 6800,	 48,   5,  4,	 48,   5,  4},
    -	{12500000,  96000,	7, 8643,	 64,   8,  2,	 64,   8,  2},
    +	{ 3072000,  96000,	2, 16,   0,	 64,   8,  2,	 64,   8,  2},
    +	{ 6144000,  96000,	1, 16,   0,	 64,   8,  2,	 64,   8,  2},
    +	{12000000,  96000,	1, 8, 1920,	 64,   8,  2,	 64,   8,  2},
    +	{12000000,  96000,	1, 7, 6800,	 48,   5,  4,	 48,   5,  4},
    +	{12288000,  96000,	1, 8,    0,	 64,   8,  2,	 64,   8,  2},
    +	{12500000,  96000,	1, 7, 8643,	 64,   8,  2,	 64,   8,  2},
     	/* 176.4k rate */
    -	{12000000, 176400,	7, 5264,	 32,   8,  2,	 32,   8,  2},
    -	{12000000, 176400,	8, 4672,	 32,   6,  3,	 32,   6,  3},
    -	{12500000, 176400,	7, 2253,	 32,   8,  2,	 32,   8,  2},
    +	{ 5644800, 176400,	2, 8,    0,	 32,   8,  2,	 32,   8,  2},
    +	{11289600, 176400,	1, 8,    0,	 32,   8,  2,	 32,   8,  2},
    +	{12000000, 176400,	1, 7, 5264,	 32,   8,  2,	 32,   8,  2},
    +	{12000000, 176400,	1, 8, 4672,	 32,   6,  3,	 32,   6,  3},
    +	{12288000, 176400,	1, 7, 3500,	 32,   8,  2,	 32,   8,  2},
    +	{12500000, 176400,	1, 7, 2253,	 32,   8,  2,	 32,   8,  2},
     	/* 192k rate */
    -	{12000000, 192000,	8, 1920,	 32,   8,  2,	 32,   8,  2},
    -	{12000000, 192000,	7, 6800,	 24,   5,  4,	 24,   5,  4},
    -	{12500000, 192000,	7, 8643,	 32,   8,  2,	 32,   8,  2},
    +	{ 6144000, 192000,	2, 8,	 0,	 32,   8,  2,	 32,   8,  2},
    +	{12288000, 192000,	1, 8,	 0,	 32,   8,  2,	 32,   8,  2},
    +	{12000000, 192000,	1, 8, 1920,	 32,   8,  2,	 32,   8,  2},
    +	{12000000, 192000,	1, 7, 6800,	 24,   5,  4,	 24,   5,  4},
    +	{12288000, 192000,	1, 8,    0,	 32,   8,  2,	 32,   8,  2},
    +	{12500000, 192000,	1, 7, 8643,	 32,   8,  2,	 32,   8,  2},
     };
     
     static const char * const ldac_in_text[] = {
    @@ -261,6 +300,25 @@ static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
     static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
     	mic_select_text);
     
    +static const char * const hp_poweron_time_text[] = {
    +	"0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms",
    +	"153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" };
    +
    +static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3,
    +	hp_poweron_time_text);
    +
    +static const char * const hp_rampup_step_text[] = {
    +	"0ms", "0.98ms", "1.95ms", "3.9ms" };
    +
    +static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1,
    +	hp_rampup_step_text);
    +
    +static const char * const vol_soft_step_mode_text[] = {
    +	"fast", "slow", "disabled" };
    +
    +static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0,
    +	vol_soft_step_mode_text);
    +
     static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
     static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
     static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
    @@ -284,6 +342,16 @@ static const struct snd_kcontrol_new common31xx_snd_controls[] = {
     
     	SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
     			 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
    +
    +	/* HP de-pop control: apply power not immediately but via ramp
    +	 * function with these psarameters. Note that power up sequence
    +	 * has to wait for this to complete; this is implemented by
    +	 * polling HP driver status in aic31xx_dapm_power_event()
    +	 */
    +	SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum),
    +	SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum),
    +
    +	SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum),
     };
     
     static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
    @@ -356,6 +424,7 @@ static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
     	struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
     	unsigned int reg = AIC31XX_DACFLAG1;
     	unsigned int mask;
    +	unsigned int timeout = 500 * USEC_PER_MSEC;
     
     	switch (WIDGET_BIT(w->reg, w->shift)) {
     	case WIDGET_BIT(AIC31XX_DACSETUP, 7):
    @@ -366,9 +435,13 @@ static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
     		break;
     	case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
     		mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
    +		if (event == SND_SOC_DAPM_POST_PMU)
    +			timeout = 7 * USEC_PER_SEC;
     		break;
     	case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
     		mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
    +		if (event == SND_SOC_DAPM_POST_PMU)
    +			timeout = 7 * USEC_PER_SEC;
     		break;
     	case WIDGET_BIT(AIC31XX_SPKAMP, 7):
     		mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
    @@ -388,9 +461,11 @@ static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
     
     	switch (event) {
     	case SND_SOC_DAPM_POST_PMU:
    -		return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
    +		return aic31xx_wait_bits(aic31xx, reg, mask, mask,
    +				5000, timeout / 5000);
     	case SND_SOC_DAPM_POST_PMD:
    -		return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
    +		return aic31xx_wait_bits(aic31xx, reg, mask, 0,
    +				5000, timeout / 5000);
     	default:
     		dev_dbg(component->dev,
     			"Unhandled dapm widget event %d from %s\n",
    @@ -709,6 +784,10 @@ aic31xx_cm_audio_map[] = {
     	{"AIF OUT", NULL, "Activate I2S clocks"},
     };
     
    +static const struct snd_soc_dapm_widget aic31xx_dapm_mclk_widgets[] = {
    +        SND_SOC_DAPM_CLOCK_SUPPLY("MCLK")
    +};
    +
     static int aic31xx_add_controls(struct snd_soc_component *component)
     {
     	int ret = 0;
    @@ -739,6 +818,13 @@ static int aic31xx_add_widgets(struct snd_soc_component *component)
     	struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
     	int ret = 0;
     
    +	if (aic31xx->mclk_handle) {
    +			snd_soc_dapm_new_controls(dapm, aic31xx_dapm_mclk_widgets, 1);
    +	} else {
    +			dev_warn(component->dev, "DAPM MCLK widgets not set\n");
    +	}
    +
    +
     	if (aic31xx->codec_type & DAC31XX_BIT) {
     		ret = snd_soc_dapm_new_controls(
     			dapm, dac31xx_dapm_widgets,
    @@ -840,7 +926,7 @@ static int aic31xx_setup_pll(struct snd_soc_component *component,
     		   there may be trouble. To fix the issue edit the
     		   aic31xx_divs table for your mclk and sample
     		   rate. Details can be found from:
    -		   http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
    +		   https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
     		   Section: 5.6 CLOCK Generation and PLL
     		*/
     	}
    @@ -848,7 +934,7 @@ static int aic31xx_setup_pll(struct snd_soc_component *component,
     
     	/* PLL configuration */
     	snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
    -			    (aic31xx->p_div << 4) | 0x01);
    +			    (aic31xx->p_div << 4) | aic31xx_divs[i].pll_r);
     	snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
     
     	snd_soc_component_write(component, AIC31XX_PLLDMSB,
    @@ -879,7 +965,7 @@ static int aic31xx_setup_pll(struct snd_soc_component *component,
     
     	aic31xx->rate_div_line = i;
     
    -	dev_dbg(component->dev,
    +	dev_err(component->dev,
     		"pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
     		aic31xx_divs[i].pll_j,
     		aic31xx_divs[i].pll_d,
    @@ -901,6 +987,7 @@ static int aic31xx_hw_params(struct snd_pcm_substream *substream,
     			     struct snd_soc_dai *dai)
     {
     	struct snd_soc_component *component = dai->component;
    +	struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
     	u8 data = 0;
     
     	dev_dbg(component->dev, "## %s: width %d rate %d\n",
    @@ -932,6 +1019,16 @@ static int aic31xx_hw_params(struct snd_pcm_substream *substream,
     			    AIC31XX_IFACE1_DATALEN_MASK,
     			    data);
     
    +	/*
    +	 * If BCLK is used as PLL input, the sysclk is determined by the hw
    +	 * params. So it must be updated here to match the input frequency.
    +	 */
    +	if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) {
    +		aic31xx->sysclk = params_rate(params) * params_width(params) *
    +				  params_channels(params);
    +		aic31xx->p_div = 1;
    +	}
    +
     	return aic31xx_setup_pll(component, params);
     }
     
    @@ -1043,7 +1140,8 @@ static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
     	case SND_SOC_DAIFMT_I2S:
     		break;
     	case SND_SOC_DAIFMT_DSP_A:
    -		dsp_a_val = 0x1; /* fall through */
    +		dsp_a_val = 0x1;
    +		fallthrough;
     	case SND_SOC_DAIFMT_DSP_B:
     		/*
     		 * NOTE: This CODEC samples on the falling edge of BCLK in
    @@ -1088,7 +1186,7 @@ static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
     	struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
     	int i;
     
    -	dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
    +	dev_err(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
     		__func__, clk_id, freq, dir);
     
     	for (i = 1; i < 8; i++)
    @@ -1114,6 +1212,7 @@ static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
     	snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
     			    clk_id << AIC31XX_PLL_CLKIN_SHIFT);
     
    +	aic31xx->sysclk_id = clk_id;
     	aic31xx->sysclk = freq;
     
     	return 0;
    @@ -1217,6 +1316,13 @@ static int aic31xx_power_on(struct snd_soc_component *component)
     		return ret;
     	}
     
    +	/*
    +	 * The jack detection configuration is in the same register
    +	 * that is used to report jack detect status so is volatile
    +	 * and not covered by the cache sync, restore it separately.
    +	 */
    +	aic31xx_set_jack(component, aic31xx->jack, NULL);
    +
     	return 0;
     }
     
    @@ -1312,8 +1418,19 @@ static int aic31xx_codec_probe(struct snd_soc_component *component)
     	if (ret)
     		return ret;
     
    +	/* set output common-mode voltage */
    +	snd_soc_component_update_bits(component, AIC31XX_HPDRIVER,
    +				      AIC31XX_HPD_OCMV_MASK,
    +				      aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT);
     	return 0;
     }
    +static int aic31xx_of_xlate_dai_id(struct snd_soc_component *component,
    +				   struct device_node *endpoint)
    +{
    +	/* return dai id 0, whatever the endpoint index */
    +	return 0;
    +}
    +
     
     static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
     	.probe			= aic31xx_codec_probe,
    @@ -1324,6 +1441,7 @@ static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
     	.dapm_widgets		= common31xx_dapm_widgets,
     	.num_dapm_widgets	= ARRAY_SIZE(common31xx_dapm_widgets),
     	.dapm_routes		= common31xx_audio_map,
    +	.of_xlate_dai_id	= aic31xx_of_xlate_dai_id,
     	.num_dapm_routes	= ARRAY_SIZE(common31xx_audio_map),
     	.suspend_bias_off	= 1,
     	.idle_bias_on		= 1,
    @@ -1501,6 +1619,43 @@ static irqreturn_t aic31xx_irq(int irq, void *data)
     		return IRQ_NONE;
     }
     
    +static void aic31xx_configure_ocmv(struct aic31xx_priv *priv)
    +{
    +	struct device *dev = priv->dev;
    +	int dvdd, avdd;
    +	u32 value;
    +
    +	if (dev->fwnode &&
    +	    fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) {
    +		/* OCMV setting is forced by DT */
    +		if (value <= 3) {
    +			priv->ocmv = value;
    +			return;
    +		}
    +	}
    +
    +	avdd = regulator_get_voltage(priv->supplies[3].consumer);
    +	dvdd = regulator_get_voltage(priv->supplies[5].consumer);
    +
    +	if (avdd > 3600000 || dvdd > 1950000) {
    +		dev_warn(dev,
    +			 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
    +			 avdd, dvdd);
    +	} else if (avdd == 3600000 && dvdd == 1950000) {
    +		priv->ocmv = AIC31XX_HPD_OCMV_1_8V;
    +	} else if (avdd >= 3300000 && dvdd >= 1800000) {
    +		priv->ocmv = AIC31XX_HPD_OCMV_1_65V;
    +	} else if (avdd >= 3000000 && dvdd >= 1650000) {
    +		priv->ocmv = AIC31XX_HPD_OCMV_1_5V;
    +	} else if (avdd >= 2700000 && dvdd >= 1525000) {
    +		priv->ocmv = AIC31XX_HPD_OCMV_1_35V;
    +	} else {
    +		dev_warn(dev,
    +			 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
    +			 avdd, dvdd);
    +	}
    +}
    +
     static int aic31xx_i2c_probe(struct i2c_client *i2c,
     			     const struct i2c_device_id *id)
     {
    @@ -1522,6 +1677,8 @@ static int aic31xx_i2c_probe(struct i2c_client *i2c,
     			ret);
     		return ret;
     	}
    +	regcache_cache_only(aic31xx->regmap, true);
    +
     	aic31xx->dev = &i2c->dev;
     	aic31xx->irq = i2c->irq;
     
    @@ -1549,6 +1706,14 @@ static int aic31xx_i2c_probe(struct i2c_client *i2c,
     		aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;
     	}
     
    +	aic31xx->mclk_handle = devm_clk_get(&i2c->dev, "MCLK");
    +	if (IS_ERR(aic31xx->mclk_handle)) {
    +			if (PTR_ERR(aic31xx->mclk_handle) != -ENOENT)
    +					return PTR_ERR(aic31xx->mclk_handle);
    +			aic31xx->mclk_handle = NULL;
    +	}
    +
    +
     	aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",
     						      GPIOD_OUT_LOW);
     	if (IS_ERR(aic31xx->gpio_reset)) {
    @@ -1569,6 +1734,7 @@ static int aic31xx_i2c_probe(struct i2c_client *i2c,
     				"Failed to request supplies: %d\n", ret);
     		return ret;
     	}
    +	aic31xx_configure_ocmv(aic31xx);
     
     	if (aic31xx->irq > 0) {
     		regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1,
    diff --git a/sound/soc/codecs/tlv320aic31xx.h b/sound/soc/codecs/tlv320aic31xx.h
    index cb024955c..007522a88 100644
    --- a/sound/soc/codecs/tlv320aic31xx.h
    +++ b/sound/soc/codecs/tlv320aic31xx.h
    @@ -2,7 +2,7 @@
     /*
      * ALSA SoC TLV320AIC31xx CODEC Driver Definitions
      *
    - * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
    + * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
      */
     
     #ifndef _TLV320AIC31XX_H
    @@ -118,7 +118,7 @@ struct aic31xx_pdata {
     #define AIC31XX_PLL_CLKIN_MASK		GENMASK(3, 2)
     #define AIC31XX_PLL_CLKIN_SHIFT		(2)
     #define AIC31XX_PLL_CLKIN_MCLK		0x00
    -#define AIC31XX_PLL_CLKIN_BCKL		0x01
    +#define AIC31XX_PLL_CLKIN_BCLK		0x01
     #define AIC31XX_PLL_CLKIN_GPIO1		0x02
     #define AIC31XX_PLL_CLKIN_DIN		0x03
     #define AIC31XX_CODEC_CLKIN_MASK	GENMASK(1, 0)
    @@ -151,8 +151,8 @@ struct aic31xx_pdata {
     #define AIC31XX_WORD_LEN_24BITS		0x02
     #define AIC31XX_WORD_LEN_32BITS		0x03
     #define AIC31XX_IFACE1_MASTER_MASK	GENMASK(3, 2)
    -#define AIC31XX_BCLK_MASTER		BIT(2)
    -#define AIC31XX_WCLK_MASTER		BIT(3)
    +#define AIC31XX_BCLK_MASTER		BIT(3)
    +#define AIC31XX_WCLK_MASTER		BIT(2)
     
     /* AIC31XX_DATA_OFFSET */
     #define AIC31XX_DATA_OFFSET_MASK	GENMASK(7, 0)
    @@ -232,6 +232,14 @@ struct aic31xx_pdata {
     #define AIC31XX_HSD_HP			0x01
     #define AIC31XX_HSD_HS			0x03
     
    +/* AIC31XX_HPDRIVER */
    +#define AIC31XX_HPD_OCMV_MASK		GENMASK(4, 3)
    +#define AIC31XX_HPD_OCMV_SHIFT		3
    +#define AIC31XX_HPD_OCMV_1_35V		0x0
    +#define AIC31XX_HPD_OCMV_1_5V		0x1
    +#define AIC31XX_HPD_OCMV_1_65V		0x2
    +#define AIC31XX_HPD_OCMV_1_8V		0x3
    +
     /* AIC31XX_MICBIAS */
     #define AIC31XX_MICBIAS_MASK		GENMASK(1, 0)
     #define AIC31XX_MICBIAS_SHIFT		0