Hi,
I'm refactoring our TLV320AIC3100 driver and I noticed that Figure 7-13. Clock Distribution Tree on page 64 (SLAS667C) shows that AOSR can be set between 1 - 1024 but the actual register (page 0, register 20) seems to have options for values 256, 128, 64 & 32, and everything else reserved. Table 7-24. PLL Example Configurations on page 68 even shows AOSR being 104 on one of the configurations.
Is the AOSR value limited to 256, 128, 64 & 32 or not?
// Eetu