TLV320ADC6120: Slave Mode, External MCLK, PLL Enabled

Sorry, I meant FSYNC=48KHz, BCLK=2.304MHz, MCLK=18.432MHz (BCLK=48*FSYNC, MCLK=BCLK*8).

Thanks,

Shawn

Hi Arthur,

Thanks for letting me know! In the text for the clock source select it says:

Audio root clock source setting when the device is configured with
the PLL disabled in the auto clock configuration for slave mode
(AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source
1d = MCLK (GPIO or GPIx) is used as the audio root clock source
(the MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting)

in particular it says the PLL is disabled for this setting. Does it also work with the PLL enabled?

Thanks,

Shawn

Hi Arthur,

 I didn't see a WCLK in the data sheet, so I am not sure where that comes from. It would be nice if they added a block diagram of the clock chain for master and slave modes.

Thanks,

Shawn

Hi Arthur,

 I installed the PurePath software for the part. It looks like you can use MCLK as the input to the PLL in slave mode according to the block diagram given under Audio Serial Bus, Auto Clock Configuration, Configure PLL. It also looks like the MCLK frequency is very flexible which is a great feature considering the current semiconductor part shortages. 

Thanks,

Shawn