TLV320ADC6140: Synchronization between ADC input channels

Hello,

I would really appreciate it if someone could direct me to a relevant design document or know the answer.

BR,

Moran.

Hi Jeff,

Thanks.

Do you familiar data sheet / application note where I can get more info regards sampling according to FSYNC.

BR,

Moran.

I don't have a discrete document on TDM sampling, but this picture below should give you a better understanding of how FSync (FS in the picture) is related to sample time. In short, because all input channels are placed in a single period of FS, FS period and sampling period are equivalent. The only constraint is that Bit Clock must be fast enough to support the sample word length for the amount of channels desired.

I checked internally about simultaneous sampling with more then 1 device.

This is something automatically done inside the device. When more than one device is connected to the chain, There can be a difference of one PLL Clock Cycle which is going to be negligible for all applications(<0.02degress for 20KHz).

Can you please let me know some details about your product/project ?

Hello Sanjay,

HW :

You can find below relevant capture from our design schematic.

Please ignore all the options & DAC , consider it routed as in yellow mark --> 

NXP CPU is the master to two tlv320adc6140 that connected in daisy chain.

Currently I working on 2 EVB that provide me same configuration.

SW:

Under Linux (Alsa library) using pyAudio we'll capture all 8 channels in parallel (24bit/48K)

- Let me know if registers map needed , or something else.

BR,

Moran.

I shall reply in a short while

I noticed MIC5 to Mic 8 input on U2 are not named as a net. hence they are not connected to J3.

What is the intent of MCLK input into UI ?You can set up the ADC as a slave with BCLK and FSYNC as Inputs.

https://www.ti.com/lit/pdf/sbaa383

1) By mistake, I uploaded an old version w/o Net's name. Thanks for noticing.

2) As far as I understand, there are several options to connect multiple TLV320ADC6140, so we implement all options on our audio card.

Our default configuration: both ADCs are slaves with BCLK and FSYNC as inputs (from our IMX8M CPU). The Daisy chain is the choice for the output slots.

Regarding MCLK: If we want the ADC to be the master, "GPIO1 is configured as a master clock input (MCLK)".

Please advise if simultaneous sampling from all 8 channels can be influenced by settings (master/slave/daisy chain/mclk).

i would suggest to try with the Daisy chain .slave mode .

"slave mode" ??? who is the slave ?

Currently in my settings, the CPU is the master and the ADCs are slaves. 

That's correct. ADC s are the slaves

So regarding my question,

All channels (input) are simultaneous sampling inside each device (ADC) following FSYNC.

It is pure hardware and not depend on any settings / register .

Is it correct ?

Thanks for your support

Moran.