Hello,
We are experiencing very high output jitter at a sample rate of 192 kHz on the SPDIF or AES output. The input clocks to the chip are clean. Is there something we need to look for? We are going to hook up our evalboard once again and measure its output jitter.
The jitter is out of spec for a typical SPDIF stream and some devices cannot lock to it in its present state. Please let us know if you can find anything about this in all your ap notes or other EE notes.
Thanks!
