Hi Support team,
We found the startup timing diagram of the AVDD and FAULT signal are not correct. The statement mentioned that the FAULT way stays low until the AVDD reached the UVP, And at the reset is low, the AVDD should be disabled until the reset goes to the high state. ( AVDD should after the RESET goes high ).
And please provide a detailed explanation of the what is the pre-charge time to stabilize the DC voltage across the input AC coupling capacitors. How affect the AMP startup? And check inside the E2E forum, when the AC coupling capacitor value is higher than 1uF, the AMP may not startup. Please explain why?
Regards
Kelvin Lo