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TPA3221: Startup timing in the datasheet

Part Number: TPA3221

Hi Support team,

We found the startup timing diagram of the AVDD and FAULT signal are not correct. The statement mentioned that the FAULT way stays low until the AVDD reached the UVP, And at the reset is low, the AVDD should be disabled until the reset goes to the high state. ( AVDD should after the RESET goes high ).

And please provide a detailed explanation of the what is the pre-charge time to stabilize the DC voltage across the input AC coupling capacitors. How affect the AMP startup?  And check inside the E2E forum, when the AC coupling capacitor value is higher than 1uF, the AMP may not startup. Please explain why?

Regards

Kelvin Lo

  • Hi Kelvin

    We found the startup timing diagram of the AVDD and FAULT signal are not correct.

    Yes, seems the diagram is not correspond to the description. We can stick to the descriptions.

    what is the pre-charge time to stabilize the DC voltage across the input AC coupling capacitors

    While start up, our device need to establish the DC bias on the input AC coupling capacitors.

    How affect the AMP startup?

    If DC bias on the input AC coupling capacitors is failed to establish, our device won't be able to start up, can't work.

    when the AC coupling capacitor value is higher than 1uF, the AMP may not startup

    Larger capacitor will be much harder for our device to establish the DC bias, more easily can't startup.