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TLV320AIC3254: clock ratio

Part Number: TLV320AIC3254

Hi team,

Customer uses TLV320AIC3254. This DSP is set as a slave with the digital I2S data and clocks coming from another IC. The bit clock-to-frame sync ratio coming to the DSP is 80fs. The frame clock is a standard 48kHz, but that means the master clock is running at 3.84MHz. (In reality, they see ~4MHz.)

This is quite strange to them. They are used to a power-of-two ratio, with 64fs being common for this situation. The bit clock would then be 3.072MHz, which is familiar and comfortable, not around 4MHz.


The only thing in datasheet that is related is in the specification tables which all show MCLK = 256fs, such as this:


While the design works, it’s rather uncommon to have such a clock ratio. Can you let us know why this might be done? Is there anything special about this DSP that would make 80fs required or beneficial? And even if there is, would 64fs still work?




  • Hi Connie,

    BCLK = 80fs is unusual I agree. Typically ADCs only support up to 32 bit resolution, so it might only be working because the device is padding the 8 remaining bits with zeros in each channel. There's no real benefit to 80fs, so I would set your BCLK to 64fs: for both familiarity and that is what the datasheet is spec'd for.

    Best Regards,