TAS6424-Q1: MCLK and SCLK

Arie Li

Part Number: TAS6424-Q1
Other Parts Discussed in Thread: TAS6424, TAS6424E-Q1

Hi expert,

How to understand the description "The MCLK clock must not be in phase to sync to SCLK" in TAS6424-Q1 datasheet? Does it mean the MCLK doesn't have to be synced or edge-aligned with SCLK? Why this description is deleted in TAS6424E-Q1 datasheet? Thanks.

Arie

over 1 year ago

0 Gregg Scott over 1 year ago

TI__Mastermind 34305 points

Hello Arie,

If you read carefully, it states that the edge-alignment must not be in phase in the TAS6424-Q1. This is no longer the case in the TAS6424E-Q1.

Regards,
Gregg Scott

0 Arie Li over 1 year ago in reply to Gregg Scott

TI__Expert 3390 points

Hi Gregg,

So it means we should avoid below waveform and must add some delay between MCLK and SCLK rising edge, right? What will happen if MCLK and SCLK edge is aligned and in phase? How to make sure in system that the MCLK and SCLK are not in-phase? It can be controlled by the I2S master? Thanks.

Arie

0 Gregg Scott over 1 year ago in reply to Arie Li

TI__Mastermind 34305 points

Arie,

My recommendation is to use the TAS6424E-Q1. It is a newer device with improvements, especially in EMI. To answer your question, yes, you need to misalign the MCLK and SCLK in the TAS6424-Q1.

Regards,
Gregg Scott

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TAS6424-Q1: MCLK and SCLK