TLV320AIC3206：For pins not used in TLV320AIC3206

Nakano Yuma

Prodigy 30 points

Part Number: TLV320AIC3206

Hi.

I would like to use TLV320AIC3206 as follows.

1 input, 1 output (microphone not used)
SPI is not used
No headphones

Under these conditions, is it OK if all unused pins are floating?
I am thinking of floating the following pins.

IN2_L ,IN2_R,IN3_L,IN3_R,MICBIAS,MIC_DET,
MFP3,MFP4,MFP5,HPL,HPR,GND_SENSE

Best regards.

over 2 years ago

+1 Elizabeth Weichel over 2 years ago

TI__Prodigy 300 points

Hello,

Inputs IN2_L, IN2_R, IN3_L, IN3_R should be grounded with a 0.47uF cap; GND_SENSE should be directly tied to ground.
In registers 52-56, the multifunction pins can be disabled when not in SPI mode, so those can be left floating.
MIC_DET can be disabled in register 67 so it can be left floating.
MICBIAS, HPL, and HPR are outputs, so they can be left floating.

Best regards,

Elizabeth

0 Nakano Yuma over 2 years ago in reply to Elizabeth Weichel

Prodigy 30 points

Thank you for your response.

Additional question.
The audio input pins IN1_L and IN1_R must be input to the TLV320AIC3206 before
Is it OK to have the signal level adjusted by a transistor or something else before inputting to the TLV320AIC3206?

+1 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi,

Yes it is okay to adjust the signal level before the device. However refer to section 8.5 in the datasheet so that you do not amplify the signal beyond full scale voltage.

Best regards,

Jeff

0 Nakano Yuma over 2 years ago in reply to Jeff McPherson

Prodigy 30 points

Thank you for your response.

Please tell me the current consumed by each power supply block (IOVDD, DVDD, AVDD, VSYS)

0 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Nakano-san,

I will need to check with our design team on if this data is available. I will reply again once I hear from design team.

Thank you for your patience,

Jeff

0 Nakano Yuma over 2 years ago in reply to Jeff McPherson

Prodigy 30 points

Thank you for your response.

Clock (24.576 MHZ) is supplied externally.
Is it possible to set the following in TLV320AIC3206?
MCLK : 2.048MHz
Fs : 8KHz
BCLK : 512kHz

0 Nakano Yuma over 2 years ago in reply to Nakano Yuma

Prodigy 30 points

Additional question.

Before the analog audio input pins on the TLV320AIC3206
I would like to be able to adjust the signal level by inserting a circuit like the one in the attached file (whichever circuit I employ).
Is this a problem in terms of the rating of the TLV320AIC3206?

0 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi Nakano,

To answer your earlier question, the application reference guide has information on power consumption in different modes, does that answer what you need to know? https://www.ti.com/lit/an/slaa463b/slaa463b.pdf?ts=1656385649830&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV320AIC3206

For clock configuration refer to 2.3.3.3 in the reference guide: https://www.ti.com/lit/an/slaa463b/slaa463b.pdf?ts=1656432656065

If you supply a 24.576 clock, then that is MCLK, not 2.048MHz. From there you can use the dividers referring to this tool to calculate them: https://www.ti.com/lit/zip/slar163

Best regards,

Jeff

0 Nakano Yuma over 2 years ago in reply to Jeff McPherson

Prodigy 30 points

Hi Jeff

Thank you for your response.

Thank you for providing the material.

I have a question regarding 2.5.2.1 through 2.5.3.8.
I have found that the voltage values for DVdd and AVdd were specified.
but not for Vsys.
As for 2.5.2.1 through 2.5.3.8, does it depend on the value of Vsys?
I am planning to set Vsys to 3.3V currently.

Also, I am thinking of installing a low-pass filter on the audio output pin, is this a problem with the specifications?

Best regards.

+1 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi Nakano,

Today is a TI Holiday and our experts are out of office. Please give us another day to look at and answer your question. For record keeping purposes please do not reply to this message unless 48 hours have passed without a response.

Thank you for your patience,

Jeff

+1 Jeff McPherson over 2 years ago in reply to Jeff McPherson

TI__Mastermind 33015 points

Hi Nakano,

Since 2.5.2.1-8 refers to the digital processing blocks, it's unlikely Vsys makes an impact here. However all of the performance specs are taken with 1.8V Vsys/AVDD/DVDD. 3.3V should be fine as long as your AVDD and DVDD are also at least 3.3V.

A low pass filter on the output theoretically is fine if for some reason you wanted to remove parts of the sampling band.

Best regards,

Jeff

0 Nakano Yuma over 2 years ago in reply to Jeff McPherson

Prodigy 30 points

Hi Jeff

Thank you for your response.

I asked you a while ago about the current consumption of each power supply block.
I was able to figure out the current consumption of AVDD and DVDD from the information you gave me.

However, I couldn't find any specific information about the current consumption of IOVdd and Vsys (I was able to confirm that the current consumption of IOVdd depends on the digital input/output pins.)

Can you tell me the current consumption when 3.3V is supplied to IOVdd and Vsys in general use?

I have a later question regarding the power on sequence.
I checked the documentation you gave me and found that the rise time is Vsys, IOVdd, DVdd.
DVdd_CP, AVdd, and DRVdd_HP in that order.
Assuming Vsys and IOVdd as 3.3V, DVdd and DVdd_CP as 1.8V, and AVdd and DRVdd_HP as 1.8V
The power supply sequence assumes that 3.3V of Vsys and IOVdd rise first.
Is there any problem if 1.8V of DVdd.DVdd_CP and 1.8V of AVdd.DRVdd_HP are started up at the same timing?
(1.8V for DVDD.DVDD_CP and 1.8V for AVDD.DRVDD_HP are supplied from different power supply ICs)

Also, are there any regulations regarding the power supply fall sequence?

Best regards

0 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi Nakano,

I will follow up with our design team on the current consumption specs.

The application guide says that "multiple domains may be powered up at the same time" so there is no problem if 1.8V of DVdd.DVdd_CP and 1.8V of AVdd.DRVdd_HP are powered together.

For power down the best sequence is the inverse of the power up sequence.

Best regards,

Jeff

0 Nakano Yuma over 2 years ago in reply to Jeff McPherson

Prodigy 30 points

Hi Jeff

Thank you for your response.
Should I strictly follow the sequence when the power is turned off?

Best regards

0 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi Nakano,

It is best practice to follow power of and off sequencing.

Best regards,

Jeff

0 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi Nakano,

Our design team let me know that Vsys and IOVDD will be only a few mA. IOVDD will depend on switching and I/O behavior but static behavior will be very small. Vsys is a peripheral supply so it's current draw is probably a mA or less.

Best regards,

Jeff

0 Nakano Yuma over 2 years ago in reply to Jeff McPherson

Prodigy 30 points

Hi Jeff

Thank you for your response.

If the TLV320AIC3206 is used as follows
Please tell me how much current is consumed by each power supply block.

1 input, 1 output (microphone not used)
SPI is not used
No headphones

Best regards.

0 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi Nakano,

We don't have that kind of specific use case information. The application guide (2.5.2 and 2.5.3) will help give you an estimate by telling you the power consumption based on your signal path set up.

Best regards,

Jeff

0 Nakano Yuma over 2 years ago in reply to Jeff McPherson

Prodigy 30 points

Hi Jeff

Thank you for your response

I have a question regarding audio input/output.

For example, if you input audio at 0.5Vpp to the input, the
With the default register settings, the audio output will also be close to 0.5Vpp
will the audio output also be close to 0.5Vpp?

Best regards,

0 Jeff McPherson over 2 years ago in reply to Nakano Yuma

TI__Mastermind 33015 points

Hi Nakano,

By default there will be no connections made so some settings will have to be written. But you can use the analog bypass path, and with 0 gain applied you should get something close to the same input you put in.

Best regards,

Jeff

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TLV320AIC3206：For pins not used in TLV320AIC3206