TAS5508B MCLK SCLK LRCLK VALID signal

Hi, Ed,

I'm not an expert on the TAS5508B, but let me give you my $0.02:

1) yes, that's fine

2) see page 54 of the d/s

3) is your customer reading an error in this register, or is it 0? Note, this is a "sticky" register which means it keeps the error bit set even after the error goes away. We usually write to the register to clear the sticky bits, and then read it to clear any potentially flakey stuff at start-up or anything. What is BKND_ERR doing?

-d2

Hi, Don.

I'm Ed's customer.

Our goal is to run at 44.1 KHz sample rate with MCLK = 256*fs.

I've verified MCLK at 11.289 MHz, LRCLK at 2.822 MHz, SCLK at 44.1 KHz.  LRCLK and SCLK are synchronized on their falling edges.

I am writing 0x4C to the control register (addr 0x00), and 0x000000B0 to the master volume register (addr 0xD9).  Other than that, I am using default register settings.

The /BKND_ERR is held high from before the 5508 is brought out of reset, and never goes low.

I am reading 0x00 from the err status register (addr 0x02), but the VALID signal never goes high.

Do I need to change any other registers from the defaults?  Any other thoughts?

Thanks,

-Rob

Hi, Rob,

I am not super familiar with the TAS5508B, but I have highlighted your question to the responsible team.

-d2

Hi Rob,

I'll see if I can find out more info. about the error status register.

Regards,
Lester Longley

Hi Rob,

For reference, excerpting the error-status register description from the TAS5508B datasheet (http://www.ti.com/lit/gpn/tas5508b):

3.1.2 Error Status Register (0x02)

• No internal errors (the valid signal is high)
• A clock error has occurred – These are sticky bits that are cleared by writing to the register.

  • LRCLK error – when the number of MCLKs per LRCLK is incorrect
  • SCLK error – when the number of SCLKS per LRCLK is incorrect
  • Frame slip – when the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
  • PLL phase-lock error

This above list seems to correlate with the following definitions I located in a file "pwm.h":

//
// PWM_REG_ERROR_STATUS
//
#define ERROR_STATUS_NO_ERRORS      0x00
#define ERROR_STATUS_FRAME_SLIP     (1 << 3)
#define ERROR_STATUS_LRCLK          (1 << 4)
#define ERROR_STATUS_SCLK           (1 << 5)
#define ERR0R_STATUS_PLL_AUTO_LOCK  (1 << 6)
#define ERROR_STATUS_CLIP           (1 << 7)

#define ERROR_STATUS_DEFAULT        ERROR_STATUS_NO_ERRORS

I don't have a way to be 100% sure that these bit positions correspond to the information in the datasheet, but it seems probable to me, and I thought I should share with you, in the hope that this is helpful to you in your development/debug.

Regards,
Lester Longley