Hello team,
I've a question on the behaviour of the SRC block RDy pin.
In my application the portA is slave and used to receive an I2S signal that can be present or not (not present means no BCLK, no LRCLK), DIR ch0 is also used as AES/EBU input and portB is the I2S output. The SRC output drives the portB while the input of the SRC, is selected on the fly by the host through the register 0x2D.
I select the DIR input and everything works fine: if I attach a digital audio signal to the ch0 input, I see the signals LOCK (from DIR PLL) and RDY (from SRC) be asserted, when I detach the signal both the LOCK and DIR are de-asserted.
In this scenario, if I try to change the source of the SRC to the portA when the relevant I2S input stream is not present, the state of RDY, if already asserted, doesn't return to de-asserted. My guess was that when the input source of SRC was missed, the RDY signal would be de-asserted, but in this case the chip doesn't do that.
This point is not explictly stated on the datasheet, please could you give me some details?
Thank you very much in advance,
Marco.
