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TAS2560EVM: TAS2560EVM Changing I2S settings

Part Number: TAS2560EVM
Other Parts Discussed in Thread: TAS2560

I would like to use the TAS2560EVM to send I2S data to the TAS2560 at a different sample rate. Is it possible? I believe the default rate it is sending to the TAS2560 is 48 kHz.

In our custom application, we would be sending 16 kHz sample rate audio. Can I test this using the EVM?

Additionally, what are the correct settings for sending audio only via BCLK (MCLK left floating) at 16kHz?

Using the Create Dump File, the output seems incorrect:

During testing, I had to set register 0x0F to 0x00 to get audio via BCLK. However the audio is degraded and sounds more muffled with high gain noise, as if someone turned up to max volume, but voice portion was only half way.

I noticed changing setting PLL ICTRL to 1 helped, but I don't see documentation on what that register does (in the datasheet):

Thank you for your help.

  • Hi Du Lo,

    I have the EVM on hand and can troubleshoot it tomorrow under the same conditions. Can you clarify that your target audio clock frequency is 1.56Mhz?

    Kind Regards,

  • Using the EVM, I'm not sure where I can change that. Currently, using an oscilloscope to measure, I see BCLK from the EVM showing up as 3.07MHz.

    Using the formula BCLK = WS * Word Count * Word Length = 16 kHz * 2 * 16 bit = 512 kHz. This should be my BCLK on my custom board. It would be helpful if I could simulate this using the EVM. Please let me know if my math and/or formula for BCLK is off.


    Thank you,

  • Hi Du,

    Your formula is correct. In addition, I ran the EVM in the same conditions and had similar bad audio playback, you must increase your sample frequency to align with one of the clock frequencies shown in the drop down menu to get clear audio.

    Regards,

  • Is it possible to increase the sample frequency with this EVM?

  • Hi Du,

    Looking into it further, 16kHz should be supported, please allow me another day to configure the PLL registers in such an order that plays acceptable audio.

    Thank you for your patience.

  • Hi Du,

    After thorough testing on EVM and an external I2S source, we can confirm the following points to consider during PLL calculation:

    • 16kHz sampling rate is supported, however a minimum frequency on BCLK is required
    • The output of PLL has to be 3072*FS, which in this case is equal to 49.152MHz
    • Based on the above, and the fact that PLL_J can only be as high as 63, a BCLK frequency of 512kHz is not supported
    • As an example, if BCLK is increased to 1.536MHz meaning 2 channels, 48-bit per channel (actual data bits can still be 16-bit with 32-bit offset bits), then PLL_J can be set to 32 and WCLK as 16kHz
    • Attached is an example register dump for the test described above
      • w 98 00 00
        w 98 7f 00
        w 98 07 41
        d 10
        w 98 00 00
        w 98 7f 00
        w 98 07 00
        w 98 00 00
        w 98 7f 00
        w 98 01 01
        d 10
        
        w 98 00 00
        w 98 7f 00
        # Specify the clock (MCLK/BCLK)
        w 98 0f 01
        # PLL P
        w 98 0f 01
        # PLL J
        w 98 10 20
        # PLL D - MSB 6 bits
        w 98 11 00
        # PLL D - LSB 8 bits
        w 98 12 00
        w 98 00 00
        w 98 7f 00
        w 98 00 00
        #decimation and interpolation
        w 98 0d 18
        w 98 0e 10
        #clock error detection
        w 98 50 31
        w 98 04 5f
        w 98 15 00
        w 98 09 83
        w 98 00 00
        w 98 7f 00
        w 98 00 fd
        w 98 36 c2
        w 98 00 00
        w 98 7f 00
        w 98 08 01
        w 98 36 31
        w 98 22 3f
        w 98 00 00
        w 98 7f 00
        w 98 49 0c
        w 98 3c 33
        w 98 02 01
        w 98 07 41
        d 10
        w 98 00 32
        w 98 28 7f
        > fb
        > b5
        > 00
        w 98 2c 80
        > 04
        > 4c
        > 00
        w 98 30 7f
        > f7
        > 6a
        > 00
        w 98 1c 7f
        > ff
        > ff
        > ff
        w 98 20 00
        > 00
        > 00
        > 00
        w 98 24 00
        > 00
        > 00
        > 00
        w 98 00 33
        w 98 18 06
        > 66
        > 66
        > 66
        w 98 00 34
        w 98 34 3a
        > 46
        > 74
        > 00
        w 98 38 22
        > f3
        > 07
        > 00
        w 98 3c 80
        > 77
        > 61
        > 00
        w 98 40 22
        > a7
        > cc
        > 00
        w 98 44 3a
        > 0c
        > 93
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 00
        w 98 7f 00
        w 98 00 33
        w 98 10 75
        > c2
        > 8e
        > 00
        w 98 14 6e
        > 14
        > 79
        > 00
        w 98 20 1e
        > 00
        > 00
        > 00
        w 98 24 21
        > 3d
        > 71
        > 00
        w 98 28 24
        > 7a
        > e1
        > 00
        w 98 2c 27
        > b8
        > 52
        > 00
        w 98 30 2a
        > f5
        > c3
        > 00
        w 98 34 2e
        > 33
        > 33
        > 00
        w 98 38 31
        > 70
        > a4
        > 00
        w 98 3c 34
        > ae
        > 14
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 32
        w 98 3c 3d
        > 99
        > 9a
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 32
        w 98 40 30
        > 00
        > 00
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 32
        w 98 44 50
        > 00
        > 00
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 32
        w 98 4c 02
        > 00
        > 00
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 32
        w 98 54 00
        > 88
        > 40
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 32
        w 98 58 00
        > 06
        > d3
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 32
        w 98 60 28
        > 00
        > 00
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 33
        w 98 40 00
        > 00
        > 00
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 00 33
        w 98 64 39
        > 80
        > 00
        > 00
        w 98 00 00
        w 98 7f 00
        w 98 07 40

    Let us know if there is any further question.

  • Thank you for the thorough explanation Daveon!

    I'll test it out. Have a great weekend!

  • Hi Daveon,

    Could you tell me what you used for your I2S external source? If it's a dev kit from TI that I can purchase to configure, that would be ideal.

    I'm trying to see what is the quickest path to replicate your testing.

    Thank you,

    Du

  • Hi Du,

    The external I2S source equipment we use is for extensive lab testing (APx555), and we're not aware of any TI platform that supports multiple sampling rates and clock ratios.

  • Thank you very much for the fast response and support!