TAS5806MD: What is the latency from SDIN to SOUT, in SCLK cycles?

Michael Lewis80

Part Number: TAS5806MD

We have SCLK, LRCLK, and SDIN coming from the host to the TAS5806.

We have SCLK, LRCLK, and SDOUT going to an AEC microphone array chip. (XMOS XVF3510).

Since SCLK and LRCLK are not passed through the TAS5806, we assume that SDOUT is synchronized with them such that the above implementation is correct.

If so then SDOUT for a stereo 32-bit audio stream would be delayed by an integer multiple of exactly 64 SCLKs, correct?

Can that be confirmed?

over 1 year ago

0 Shadow He over 1 year ago

TI__Mastermind 35490 points

Hi Michael

We need some time to confirm it, the design team is on National holiday until 8th this month. I think the delay will be a little longer than 64 SCLKs.

0 Shadow He over 1 year ago

TI__Mastermind 35490 points

Hi Michael

If you set the SDOUT signal pre-DSP, will get the minimum delay, it's 4 Fs clock, that is to say 256 SLCKs. The delay mostly happens on the input and output buffer.

+1 Michael Lewis80 over 1 year ago in reply to Shadow He

Prodigy 10 points

Thanks. And if it is post-DSP i presume it is longer but still a multiple of 64 SCLK. Would that delay be affected by any settings, such as EQ stages?

+1 Shadow He over 1 year ago in reply to Michael Lewis80

TI__Mastermind 35490 points

Hi Michael

Yes, by different DSP function settings, there's additional delay happens inside of DSP. It's hard to tell for every conditions.

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TAS5806MD: What is the latency from SDIN to SOUT, in SCLK cycles?