TAS6422E-Q1: GVDD abnormal voltage step in startup

Hi Johnny

    The STANDBY pin will affect the behavior of the GVDD, which is the inner LDO output. I think we needn't pull down STANDBY pin along power up. We could try release the STANDBY pin at the very beginning, then power up to check the results.

I put STANBY pin always on high level, which is connected to MCU_3V3. The startup waveform of GVDD is the same.

Hi Johnny

    The waveform at my side is different from yours. The GVDD rise quickly and didn't form a stair at 5V. Could we please double check the power supply like PVDD or DVDD at your side. And maybe find out what we do during this 5V stair. Like I2S signal, I2C command, GPIO port. But in general, we think it shouldn't affect using since the voltage could reach the final value.

The level state of GVDD depends on the state of Mute, and when Mute is high, GVDD will lift to produce steps. Is that so, please?

Hi Zhenyi

   This also shouldn't be a normal behavior. I captured the waveform at my side. The GVDD is not related with MUTE pin. 

   Could we please double check there's nothing else circuit been connected to GVDD pin, only a 2.2uF capacitor, right? Also in your waveform, seems the pull up voltage for MUTE pin is smaller than 3V, could we please also check the power supply?

There's nothing else circuit been connected to GVDD pin, only a 2.2uF capacitor. The voltage of DVDD pin is 3.3V.

Hi Zhenyi

   How many board have you tested? Is this phenomenon happens to all of your board?

Yes, this phenomenon happens on all boards. May I ask if you also tested the TAS6422E, not the TAS6422? Is GVDD also powered later than DVDD?

Hi Zhenyi

   Yes, I'm testing on the TAS6424E EVM. The PVDD and VDD need to both get power supply first, then GVDD could goes up correctly. If you have EVM at your hands, you could also have a check.

I don't have an EVM board at my hands, the design situation on my side is that VDD power on later than PVDD. Please remove VDD power supply to see if the GVDD voltage is only about 5.6V. In addition, will the upper stage of the GVDD order cause the chip to work abnormally?

Hi Zhenyi

   In that case, I'll try to make some change on the EVM and have a test, I think it's a possible reason. Please give me some time, I hope to provide you the results before this Friday.

Shadow,

If no change maed, will this waveform impact chip? Any risk? If no, I think we can keep the design.

Thanks.

Johnny

Hi Shadow

Thank you for your job on this problem analysis.