TAS2555: I2C stops ACKing ~21ms after Reset line goes high

Hi Kurt,

Thanks for sharing your detailed debugging so far, I'll list some more things to check on your setup:

• Please inspect the voltage rails supplying TAS2555 during the test, is there any droop on IOVDD or VREG?
• Please also inspect SPI_SEL pin as well as ADR1 and ADR0 pins, is there any change on these pins?
• What is your I2C frequency? Have you tried different speeds eg 100kHz and 400kHz?
• Once you get NACK back from TAS2555, could you try the rest of the possible I2C addresses? Even if you don't change the hardware connection on those pins, I'd like to double check if the address could be changing.

Let me know if you have any questions.

Best regards,
-Ivan Salazar
Applications Engineer

Ivan, thank you, it was the power rails.  The power rail switches were improperly loaded with N type FETs instead of P type, so the voltage was lower and not sequenced.  Replacing those with the correct parts fixed the I2C problem.

One other question regarding this application: Following the device setup as detailed in 9.5.2, should the device be able to receive 32 bit I2S data without any more configuration?

Hi Kurt,

Thanks for letting us know what the problem was on your setup.

Regarding section 9.5.2, yes you should be able to play audio using that script. Just consider that the last part of the script is the power down sequence, you shouldn't include that part.
What are your clock settings? ie. MCLK, BCLK and WCLK frequencies? You may also use PPC3 to generate a configuration specific for your application requirements.

Best regards,
-Ivan Salazar
Applications Engineer

Ivan,

MCLK = 12.5MHz, BCLK = 3.125MHz, WCLK = 48.828KHz.

Currently the I2S data is a ~254Hz triangle wave of 32 bit data from 0 to 192,000,000.  In addition to what's in the script, I've also set 0,0,42 to 0x04 and 0.1.1 to 0x18 as the I2S data is a single stream of 32 bit data.

The speaker output I'm getting into an 8 ohm speaker (the one from the dev kit) is a 195KHz periodic consisting of evenly spaced positive and negative pulses. I've looked at registers 0.0.100, 0.0.104, 0.0.108 during the I2S streaming and they all look as I would expect.

Hi Kurt,

The output driver of TAS2555 is a Class-D amplifier, thus you should expect a PWM signal, however if the duty cycle is not changing, that would mean it is idle and not playing audio for some reason.
Let me generate a configuration file based on your system clocks and other descriptions, I'll share that later today.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Kurt,

Can you try with the attached script? I generated this using PPC3 based on BCLK = 3.072MHz input to PLL and 48kHz sample rate (closest match to your described values).

48k_3M072_TuningMode_combined_configuration_0_TuningMode_48KHz.cfg

Section 9.5.2 is described for MCLK = 24.576MHz, which may be the reason why it's not working on your system.

Best regards,
-Ivan Salazar
Applications Engineer

Ivan,

Thanks for the info.

The first thing I tried was a 25MHz MClk, but I .

I'm trying to use the .cfg file you sent but I'm confused on some things.

I don't have the ability to just play the script into the 2555 so I'm translating the pertinent parts into my C code.  Doing so, I notice some register writes that don't make sense to me.  For example in the section below, I've annotated where it appears to me to be writing to several reserved registers. My TAS2555 datasheet is dated August 2015 - revised Feb 2019

Hi Kurt,

There are some registers that were not disclosed publicly in the data sheet, however the script generated from PPC3 should work.

• You mentioned to use 25MHz before, now it is 12.5MHz, did any of the other frequencies change ie. BCLK and WCLK?
• Have you tried with the previous script (Section 9.5.2) at both previous and new clock settings? Is there any difference?
  
• have you tried with other type of signals? Or you've been only testing with triangle waveform so far?

Best regards,
-Ivan Salazar
Applications Engineer

Ivan,

The output is modulating but it is just noise.  The characteristic of the noise changes based on my MClk frequency (I've used 25MHz, 12.5MHz, 8.333MHz, audible noise at 8.333MHz MClk), but the I2S input has no effect on the output, even an I2S input of zero produces the same noise.

I don't have the ability to use the PPC3 generated script.

I am trying to generate a 4KHz sine wave.

Hi Kurt,

So you mean the noise is only present for 8.33MHz MCLK case, but you don't have output signal in any case anyways. Is that correct?
Can you comment about BCLK? Is it changing for each different case? Or is it MCLK the only one changing?
Are you using the same configuration I shared before?

Best regards,
-Ivan Salazar
Applications Engineer

Ivan,

I would like to step back from the configuration file and get more basic and describe what I'm seeing.

BCLK = 6.25MHz, WCLK = 97.656KHz.  I2S data is a sine wave, although up to this point the I2S data hasn't made any difference.  If I generate MCLK from the same base clock, with a speed of 25MHz (close to WCLK * 256), I get 196KHz pulses with no modulation.  If I generate MCLK from a different clock source with the frequency = 256 times WCLK, I get significant modulation with a nasty looking wave that generates white-ish noise. It makes no difference what the I2S data is, as long as the I2S clocks are present. With no I2S data, there is no output.

My first question, is it a requirement that the I2S clocks are all sourced from the same base clock? There's a suggestion in the datasheet to do so, but is it a requirement?

Second question, are there diagnostic/error registers?

Hi Kurt,

At least WCLK and BCLK should come form the same source, these two clocks should be direct multiples and synced, as each bit (BCLK) is sampled within a word (WCLK).
In any case, if there's a change in clocks, you must make sure that the ratio between clocks and the selected configuration is the same, otherwise you'll need to use different configuration to match the new clock ratios.

There are several flags, including clock error. Some related sections from D/S are listed below:

• Section 9.3.10.1.4 Clocking Faults: https://www.ti.com/lit/ds/symlink/tas2555.pdf#page=22&zoom=100,0,800
• Section 9.3.10.4 IRQ and Flags: www.ti.com/.../tas2555.pdf
• Page 0 Register 0x2C: https://www.ti.com/lit/ds/symlink/tas2555.pdf#page=46

Best regards,
-Ivan Salazar
Applications Engineer