PCM1820: Clock Jitter immunity

Shall reply Monday

You mean that the PCM1820 Receives  BCLK from a Source that has Jitter?

Yes.  So we are receiving digital audio that we need to recover a clock source from.  This recovered clock will be used for the PCM1820.  The recovered clock, due to many factors could have a maximum jitter of 5.5ns.  

This is something I would suggest to try out in your setup.

What is your BCLK?

The BCK /LRCK Ratio is generally measured realtime to configure the internal clocking. 

In a case where BCLK is High for eg 24.578 Mhz , a 5ns time addition will result in the clock becoming 22Mhz. The automatic circuitry is looking for a BCLK/LRCK Ratio to make internal decisions. It looks that this is above 18Mhz so an incorrect decision may not happen.

On the other hand the Highest BCLK Frequency allowed is 25Mhz and a 5 ns Jitter would make this go above 25Mhz.

The variation in the jitter  with tim and its effect on the behaviour have to be checked in the real system.

I think if you choose a Low BCLK Frequency for example 12.288Mhz 5ns jitter will be better tollerated.

At this moment this is the best answer I can offer. 

Thanks Sanjay!  Do you know if jitter will impact audio due to jitter in the sample rate?  Or does the low jitter PLL remove this?

What is the BCLK Frequency in your application?

3.072 Mhz

In this situation i think 5ns jitter is a small percentage of the BCLK Time and should not cause issues