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TAS5558: Reduce latency and improve EMI

Part Number: TAS5558
Other Parts Discussed in Thread: TAS5634

Hi,

I'm working on an amplifier which is digitally sourced via I2S. As pwm interface I use the TAS5558. The amps are 4 pieces of TAS5634 in PBTL. I have a few questions concerning both devices.

1. TAS5634: What is the modulation limit? In the test conditions 97,64 % are mentioned.

2. TAS5558: Our input sample rate is 48 kHz. We just need the conversion from I2S to pwm. What are the options to minimize latency of TAS5558? Can ASRC and DSP be bypassed?

3. TAS5558: Is there any option to set different phases for the channels to improve EMI behaviour? Are there any other options to reduce EMI?

Kind regards,
Markus

  • Hi Markus

    1. The modulation index limit is the maximum duty cycle of each PWM output waveform.

    2. you can bypass ASRC to minimize latency, but when ASRC is bypassed, the internal master clock is generated by the MCLK input, the I2S master mode must be activated in order to accept SDIN1-5。

    3. The EMI is a system issue. To reduce EMI, you can try to add LC filter at the output of TAS5634; pay attention of PCB layout for short loop; try to reduce the slew rate.

  • Hi,

    1. I know what the modulation index is, I was asking for the max. value for tas5634, because there is no info in the datasheet. Default setting of tas5558 is 93,7 %. Can I set tas5558 to the maximum duty cycle possible = 99,21 %?

    2. That means I would have to input a MCLK (at which rate?) and the tas5558 will generate the bclk and lrclk as outputs for the input data stream?

    3. I was asking for the possibilities of tas5558 to reduce EMI, e.g. a channel to channel phase shift, which is a standard feature nowadays.

    Regards,
    Markus

  • Hi Markus

    1. you can change the modulation index limit by register 0x16 0x17 0x18 0x19, the max modulation index is 99.21%。

    2. You need input a MCLK. And as it's shown in datasheet, the TAS5558 accepts master clock rates of 64, 128, 192, 256, 384, 512, and 768 Fs, the external crystal used must be 12.288 MHz from MCLK pin. While bypass ASRC, the I2S master mode must be activated, TAS5558 can provide BCLK and LRCLK by  SCLKO pin and LRCLKO pin.

    3. TAS5558  is an old device, there is no special method of device itself to reduce EMI.

  • Hi,

    1. I know the settings of tas5558. I will ask one last time: What is the maximum modulation limit of TAS5634?

    2. Let me explain the situation a bit more detailed.
    We have TAS5558 sourced by a DSP. The DSP is the master (can not be changed).
    LRCLK is 48 kHz, BCLK is 3.072 MHz, MCLK is variable (12.288 to 24.576 MHz).
    LRCLKO and BCLKO of tas5558 are unused/not connected.

    Is it possible to run the DSP core at 48 kHz (which would make the ASRC obsolete)?

    What are the possibilities to reduce the high latency (~2.65 ms)?

    Regards,
    Markus

  • 3. In the datasheet on page 70 I found the option: AD Mode - 8 Interchannel Channel Delay and Global Offset Registers (0x1B to 0x23).

    Is it possible to do a channels to channel phase shift with that option for improving EMI?

  • Hi Markus

    It’s my mistake not to read the question carefully, I feel sorry for you.

    1. For TAS5634, there is no limit for input PWM duty, but TAS5634 output PWM max duty is 97.7%. Alough you can set TAS5558 PWM max to 99.21%, but the output of TAS5634 will clip while PWM duty more than 97.7%.

    2. If you want to bypass ASRC, you need set TAS5558 I2S master mode, but for your application, it can't be achieve. You can try to change the FIFO from 32 sample to 16 sample by register 0XC4, it can reduce the FIFO latency.

    3. The interchannel Delay is used to distribute the switch current, improving harmonic distortion and cross-talk between adjacent channels. So as my understand,  it can change the PWM phase for different channel, which may help for EMI