1, register 01
Does only a transmitter not have any problem in PDALL=0, PDPA=1, PDRX=1 at time to use only time PDALL=0, PDPA=1, PDTX=1 receiver to use? Please reply it whether there is a problem (others without mention are 0)
2, register 07
What is different in making zeroing BSSL and 1 how?
The selectable thing understands TSLIP or BLOCK START as an interrupt condition, but cannot grasp what kind of phenomenon Data slip of the transmitter is.
In addition, I cannot grasp a meaning to produce an interrupt as trigger in Block start becoming the reverse choice.
In the first place I am thankful because it is unknown what kind of how to use 23 pins (/INT) assume if you can reply clearly.
3. register 0E
Does Digital Interface Receiver (DIR) mute auto when I make RXAMLL=1?
In that case, when, on the contrary, it makes RXAMLL=0, DIR will not mute auto, should it think about the case that a signal of the specifications sampling frequency out of the range was input into in RX that data may appear in DIR_OUT?
4, register 0E
Does a frequency of what Hz output it from 12 pins when I make LOL=1 when there is not RX input?
5, register 2E
64Sample comes to have a big quantity of delay, does the sound quality such as distortions improve when they compare it with 64Sample in 8Sample?
It is understood that it is for a choice of the quantity of delay, what is the merit to let you choose delay quantity daringly when you do not change for sound quality?
6, hardware
Is there the output to SRC_OUT of Fig.59 for the movement to become the automatic mute when directly connected to 11 pin (/LOCK) and 14 pin (MUTE) for hardware when there is not RX input?
7,
I want to have you reply for ignorance clearly what kind of how to use 15 pin (/RDY) assumes.
Even if it is processing to overwrite, and to set the same value to the same register in SPI control, do you not have effect to noise occurrence and sound quality?
Even if the register to set in SPI control becomes any order, do you not have any problem?