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TLV320AIC3254: Startup Issue

Part Number: TLV320AIC3254

We’re trying to get a TLV320AIC3254 codec running on a pair of custom boards. Both boards have a CC2652RSIPMOTR that are acting as masters and generating the clock lines and are using the SimpleLink Audio Plugin (v3.30.0.06). One board has a microphone attached and will be sending I2S data out, the other will have that data coming in and driving line level outputs.

[microphone]--(analog)-->[TLV320A]--(I2S)-->[CC2652]--(Wireless)-->[CC2652]--(I2S)-->[TLV320A]--(analog)-->[line out]

MCLK is 12 MHz, verified with oscilloscope and when CLKOUT is configured to route that to a GPIO (MFP5) it can also be seen.

Used the AIC3254 CS application to generate appropriate PLL_CLK values for 16k sampling; R and P of 1, J.D of 8.1920, M of 3, N of 16 and AOSR and DOSR of 128.

This is the resulting clockRegs script using those values:

    {TI3254_PAGE_0, TI3254_CLK_MUX_REG, 0x03},                          /* PLL Clock is CODEC_CLKIN */

    {TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x80 | 0x11},               /* PLL is powered up, P=1, R=1 */

    {TI3254_PAGE_0, TI3254_CLK_PLL_J_REG, 0x08},                        /* J=8 */

    {TI3254_PAGE_0, TI3254_CLK_PLL_D_MSB_REG, 0x07},                    /* D = 0780 */

    {TI3254_PAGE_0, TI3254_CLK_PLL_D_LSB_REG, 0x80},                    /* D = 0780 */

    {TI3254_PAGE_0, TI3254_CLK_NDAC_REG, 0x80 | 0x10},                  /* NDAC divider powered up, NDAC = 16 */

    {TI3254_PAGE_0, TI3254_CLK_MDAC_REG, 0x80 | 0x03},                  /* MDAC divider powered up, MDAC = 3 */

    {TI3254_PAGE_0, TI3254_DAC_OSR_MSB_REG, 0x00},                      /* DOSR = 0x0080 = 128 */

    {TI3254_PAGE_0, TI3254_DAC_OSR_LSB_REG, 0x80},                      /* DOSR = 0x0080 = 128 */

    {TI3254_PAGE_0, TI3254_CLK_NADC_REG, 0x80 | 0x10},                  /* NADC divider powered on, NADC = 16 */

    {TI3254_PAGE_0, TI3254_CLK_MADC_REG, 0x80 | 0x03},                  /* MADC divider powered on, MADC = 3 */

    {TI3254_PAGE_0, TI3254_ADC_OSR_REG, 0x80},                          /* AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A) */

with the addition of these:

    {TI3254_PAGE_0, 0x34, 0x10},

    {TI3254_PAGE_0, 0x1A, 0x80 | 0x64},

    {TI3254_PAGE_0, 0x19, 0x03},

for setting up CDIV_CLKIN, CLKOUT M, and the MPF5 GPIO.

But the GPIO just stays in its high state. If that last register, 0x19, is changed to a value of 0x00 to show the MCLK then we get a 120 kHz clock on it, as expected.

  • Hi,

    These settings look correct, the PLL_CLK should come up after 10ms.

    Can you try setting the codec to master mode and check the WCLK if you can see the 16KHz clock as this WCLK comes from PLL_CLK?

    Regards.

  • Hey,

    I swapped the codec to being master but not seeing anything on the WCLK or BCLK lines when I look at them with a scope. MCLK stayed the same, I didn't change its config and it looks the same on the scope.

    Config script changed from:
        {TI3254_PAGE_0, TI3254_SW_RESET_REG, 0x01},                         /* Reset the codec */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_1_REG, 0x00},                       /* 16bit, I2S, WCLK, BCLK is input to the device */

    to:
        {TI3254_PAGE_0, TI3254_SW_RESET_REG, 0x01},                         /* Reset the codec */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_1_REG, 0x0C},                       /* 16bit, I2S, WCLK, BCLK is output from the device */

    and the clock script has these lines added to the end:
        {TI3254_PAGE_0, TI3254_BCLK_N_DIV, 0x80 | 0x0C},                    /* BCLK divider powered up, val = 12 */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_3_REG, 0x04},                       /* Primary BCLK and Primary WCLK buffers are powered up */

    I tried it without the CLKOUT setup first and then with it routing the BCLK to the GPIO, but it also had no activity on it.

    Oh, here's some pared down schematics of the two boards (which I meant to include in the original post, sorry about the delay), of just the codec and MCU:

    Transmitter.pdfReceiver.pdf

    I've mostly been testing with a transmitter board.

    Anything else that I could try or info that could help you?

    Thanks.

  • Hi,

    That's strange, can you check if AVDD and DVDD are both present?

    You are providing LDOIN from external so you would not need DVDD/AVDD input.

    You have checked that MCU is not driving the WCLK, RESET is high and R2 is not populated - correct?

    Is this on all setup or just this one?

    Regards.

  • Hey,

    AVDD and DVDD are around 1.7v for both the transmitter and the receiver boards, measured at the caps.

    WCLK is definitely not being driven by the MCU. I checked the peripheral registers on the MCU and (as part of a test to try to bypass the whole PLL clock system, which didn’t work out) saw that the codec can generate the WCLK and BCLK lines when the CODEC_CLKIN is set to MCLK instead of PLL_CLK (just not at the correct frequency, because we can’t get the MCLK to the right frequency coming in as we would need in order to actually do things that way).

    RESET is high (3.2v to 3.3v) and R2 is not populated, correct.

    The circumstances of the original description I saw happening on another transmitter board and one of the receivers, but my testing since that has all been on a single transmitter board.

    Thanks.

  • So this is what you see - correct? WCLK and BCLK OK in the blue but not in the red with master mode.

    This is strange I will have to check on EVM as I have never seen such issue.

    I think something in the hardware setup, but if you could give me your full register configuration I can try to replicate in EVM.

  • Correct, blue path will generate both, but nothing for red when the codec is master.

    Sure, there's a fair bit in the open phase setting up some filters (converted over from a different codec), that's not standard from the plugin. This is for the transmitter (mic input) side:


    AudioHAL_I2CReg configRegs16Bit_m[] =
    {
        {TI3254_PAGE_0, TI3254_SW_RESET_REG, 0x01},                         /* Reset the codec */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_1_REG, 0x00},                       /* 16bit, I2S, WCLK, BCLK is input to the device */
    };

    AudioHAL_I2CReg clockRegs16k[] =
    {
        {TI3254_PAGE_0, TI3254_CLK_MUX_REG, 0x03},                          /* PLL Clock is CODEC_CLKIN */
        {TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x01},        /* PLL is powered up, P=1, R=1 */
        {TI3254_PAGE_0, TI3254_CLK_PLL_J_REG, 0x008},                       /* J=8 */
        {TI3254_PAGE_0, TI3254_CLK_PLL_D_MSB_REG, 0x07},                    /* Set MSB of D value D=0x0780 */
        {TI3254_PAGE_0, TI3254_CLK_PLL_D_LSB_REG, 0x80},                    /* Set LSB of D value */
        {TI3254_PAGE_0, TI3254_CLK_NDAC_REG, 0x80 | 0x10},                  /* NDAC divider powered on, NDAC = 16 */
        {TI3254_PAGE_0, TI3254_CLK_MDAC_REG, 0x80 | 0x03},                  /* MDAC divider powered on, MDAC = 3 */
        {TI3254_PAGE_0, TI3254_DAC_OSR_MSB_REG, 0x00},                      /* DOSR = 128 */
        {TI3254_PAGE_0, TI3254_DAC_OSR_LSB_REG, 0x80},                      /* DOSR = 128 */
        {TI3254_PAGE_0, TI3254_CLK_NADC_REG, 0x80 | 0x10},                  /* NADC divider powered on, NADC = 16 */
        {TI3254_PAGE_0, TI3254_CLK_MADC_REG, 0x80 | 0x03},                  /* MADC divider powered on, MADC = 3 */
        {TI3254_PAGE_0, TI3254_ADC_OSR_REG, 0x80},                          /* AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A) */
        {TI3254_PAGE_0, TI3254_BCLK_N_DIV, 0x80 | 0x0C},                    /* BCLK divider powered up, val = 12 */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_3_REG, 0x04},                       /* Primary BCLK and Primary WCLK buffers are powered up */
        {TI3254_PAGE_0, 0x34, 0x10},        /* CLKOUT on MFP5 */
        {TI3254_PAGE_0, 0x1A, 0x80 | 0x64}, /* CLKOUT M powered up and divider = 100 */
        {TI3254_PAGE_0, 0x19, 0x00},        /* MCLK on CDIV_CLKIN */
    };


    AudioHAL_I2CReg openScript[] =
    {
        /* Configure Analog I/O */
        {TI3254_PAGE_1, TI3254_PWR_CTRL_REG, 0x08},                         /* Disabled weak connection of AVdd with DVdd */
        {TI3254_PAGE_1, TI3254_LDO_CTRL_REG, 0x08 | 0x01},                  /* Analog blocks enabled, Power AVdd from LDO */
        {TI3254_PAGE_1, TI3254_ANALOG_IP_QCHRG_CTRL_REG, 0x32},             /* Analog inputs power up time is 6.4 ms */
        {TI3254_PAGE_1, TI3254_REF_PWR_UP_CTRL_REG, 0x01},                  /* Reference will power up in 40ms when analog blocks are powered up */

        /* Configure ADC */
        /* Set low-pass filter to pass everything above 1Hz (0.00045 * ADC_FS) */
        {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_N0_REG_BASE, 0x7F},         /* ADC AGC Low-pass filter Coefficient MSB N0 = 8,288,607 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N0_REG_BASE+1), 0xFF},         /* ADC AGC Low-pass filter Coefficient N0 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N0_REG_BASE+2), 0xFF},         /* ADC AGC Low-pass filter Coefficient LSB N0 */
        {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_N1_REG_BASE, 0xFF},         /* ADC AGC Low-pass filter Coefficient MSB N1 = -20,992 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N1_REG_BASE+1), 0xAE},         /* ADC AGC Low-pass filter Coefficient N1 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N1_REG_BASE+2), 0x00},         /* ADC AGC Low-pass filter Coefficient LSB N1 */
        {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_D1_REG_BASE, 0x00},         /* ADC AGC Low-pass filter Coefficient MSB D1 = 512 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_D1_REG_BASE+1), 0x02},         /* ADC AGC Low-pass filter Coefficient D1 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_D1_REG_BASE+2), 0x00},         /* ADC AGC Low-pass filter Coefficient LSB D1 */
        /* IIR filter cutoff at approx. 400 Hz */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE, 0x3A},  /* ADC C36 MSB Right Channel IIR N0 = 3,863,296 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE+1), 0xF3}, /* ADC C36 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE+2), 0x00}, /* ADC C36 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE, 0xF4},  /* ADC C37 MSB Right Channel IIR N1 = -736,512 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE+1), 0xC3},  /* ADC C37  */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE+2), 0x00},  /* ADC C37 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE, 0x50},  /* ADC C38 MSB Right Channel IIR D1 = 5,262,080 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE+1), 0x4B},  /* ADC C38  */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE+2), 0x00},  /* ADC C38 LSB */
        /* EQ filter to remove 475 Hz, 10 Hz bandwidth, -24dB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE, 0x7E},  /* ADC C39 MSB Right Channel Biquad A N0 = 8,300,800 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE+1), 0xA9},  /* ADC C39  */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE+2), 0x00},  /* ADC C39 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE, 0x81},  /* ADC C40 MSB Right Channel Biquad A N1 = -8,275,968 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE+1), 0xB8},  /* ADC C40 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE+2), 0x00},  /* ADC C40 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE, 0x7E},  /* ADC C41 MSB Right Channel Biquad A N2 = 8,289,024 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE+1), 0x7B},  /* ADC C41 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE+2), 0x00},  /* ADC C41 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE, 0x7E},  /* ADC C42 MSB Right Channel Biquad A D1 = 8,275,968 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE+1), 0x48},  /* ADC C42 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE+2), 0x00},  /* ADC C42 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE, 0x82},  /* ADC C43 MSB Right Channel Biquad A D2 = -8,201,216 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE+1), 0xDC},  /* ADC C43 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE+2), 0x00},  /* ADC C43 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE, 0x00},  /* ADC C44 MSB Right Channel Biquad A N0 = 0 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE+1), 0x00},  /* ADC C44 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE+2), 0x00},  /* ADC C44 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE, 0x40},  /* ADC C45 MSB Right Channel Biquad A N1 = 4,194,304 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE+1), 0x00},  /* ADC C45 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE+2), 0x00},  /* ADC C45 LSB */
        /* Enable filtering and set Mic bias */
        {TI3254_PAGE_8, TI3254_ADC_ADP_FILTER_CTRL_REG, 0x04},              /* Adaptive Filtering enabled for ADC */
        {TI3254_PAGE_1, TI3254_COMMON_MODE_CONTROL_REG, 0x40},              /* Full Chip Common Mode = 0.75v */
        {TI3254_PAGE_1, TI3254_MICBIAS_CTRL_REG, 0x40 | 0x20 | 0x04},       /* Mic bias power enabled, 2.075V, Source = LDOIN */
        {TI3254_PAGE_0, TI3254_ADC_SIG_P_BLK_CTRL_REG, 0x02},               /* ADC Signal Processing Block PRB_P2 */
        {TI3254_PAGE_1, TI3254_MICBIAS_CTRL_REG, 0x40},                     /* MICBIAS powered up */

        /* TI3254_LINE_IN */
        {TI3254_PAGE_1, TI3254_LEFT_MICPGA_P_CTRL_REG, 0x40},               /* IN1L is routed to Left MICPGA with 10k resistance */
        {TI3254_PAGE_1, TI3254_LEFT_MICPGA_N_CTRL_REG, 0x40},               /* CM is routed to Left MICPGA via CM1L with 10k resistance */
        {TI3254_PAGE_1, TI3254_RIGHT_MICPGA_P_CTRL_REG, 0x40},              /* IN1R is routed to Right MICPGA with 10k resistance */
        {TI3254_PAGE_1, TI3254_FLOAT_IP_CTRL_REG, 0xC0},                    /* IN1L input is weakly driven to common mode. Use when not routing IN1L to Left and Right MICPGA and HPL, HPR */

        /* Enable ADC */
        {TI3254_PAGE_1, TI3254_LEFT_MICPGA_VOL_CTRL_REG, 0x80},             /* 0.0dB */
        {TI3254_PAGE_1, TI3254_RIGHT_MICPGA_VOL_CTRL_REG, 0x0C},            /* 6.0dB with 20K impedance yields 0.0dB */

        {TI3254_PAGE_0, TI3254_LEFT_ADC_VOL_CTRL_REG, 0x68},                /* -12dB */
        {TI3254_PAGE_0, TI3254_RIGHT_ADC_VOL_CTRL_REG, 0x68},               /* -12dB */
        {TI3254_PAGE_0, TI3254_ADC_CHANNEL_SETUP_REG, 0x40},                /* Right Channel ADC is powered up, Left Channel ADC is powered down */
        {TI3254_PAGE_0, TI3254_ADC_FINE_GAIN_ADJ_REG, 0x80}                 /* Right ADC Channel Un-muted. Left Muted. Left and Right ADC Channel Fine Gain = 0dB */
    };


    AudioHAL_I2CReg startScript[] =
    {
        {TI3254_PAGE_0, TI3254_LEFT_DAC_VOL_CTRL_REG, 0x10},
        {TI3254_PAGE_0, TI3254_RIGHT_DAC_VOL_CTRL_REG, 0x10},
        {TI3254_PAGE_0, TI3254_LEFT_ADC_VOL_CTRL_REG, 0x0C},
        {TI3254_PAGE_0, TI3254_RIGHT_ADC_VOL_CTRL_REG, 0x0C}
    };

  • Oops, sorry, just noticed I grabbed the wrong configRegs script, that's for the MCU being master. This is the correct one:


    AudioHAL_I2CReg configRegs16Bit[] =
    {
        {TI3254_PAGE_0, TI3254_SW_RESET_REG, 0x01},                         /* Reset the codec */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_1_REG, 0x0C},                       /* 16bit, I2S, WCLK, BCLK is output from the device */
    };

  • Hi,

    I used your settings except the filter coefficients as shown and I am able to see the WCLK and BCLK.

    TI_EVM.txt
    w 30 00 00
    w 30 01 01
    w 30 1B 0C
    w 30 04 03
    w 30 05 91
    w 30 06 08
    w 30 07 07
    w 30 08 80
    w 30 0B 90
    w 30 0C 83
    w 30 0D 00
    w 30 0E 80
    w 30 12 90
    w 30 13 83
    w 30 14 80
    w 30 1E 8C
    w 30 1D 04
    w 30 34 10
    w 30 1A E4
    w 30 19 00
    w 30 00 01
    w 30 01 08
    w 30 02 81
    w 30 47 32
    w 30 7B 01
    w 30 00 01
    w 30 0A 40
    w 30 33 64
    w 30 00 00
    w 30 3D 02
    w 30 00 01
    w 30 33 40
    w 30 00 01
    w 30 34 40
    w 30 36 40
    w 30 37 40
    w 30 3A C0
    w 30 00 01
    w 30 3B 80
    w 30 3C 0C
    w 30 00 00
    w 30 53 68
    w 30 54 68
    w 30 51 40
    w 30 52 80
    w 30 00 00
    w 30 41 10
    w 30 42 10
    w 30 53 0C
    w 30 54 0C

    customer.txt
    AudioHAL_I2CReg configRegs16Bit[] =
    {
        {TI3254_PAGE_0, TI3254_SW_RESET_REG, 0x01},                         /* R1 Reset the codec */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_1_REG, 0x0C},                       /* R27 16bit, I2S, WCLK, BCLK is output from the device */
    };
    
    
    AudioHAL_I2CReg clockRegs16k[] =
    {
        {TI3254_PAGE_0, TI3254_CLK_MUX_REG, 0x03},                          /* R4 PLL Clock is CODEC_CLKIN */
        {TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x01},        /* R5 PLL is powered up, P=1, R=1 */
        {TI3254_PAGE_0, TI3254_CLK_PLL_J_REG, 0x008},                       /* R6 J=8 */
        {TI3254_PAGE_0, TI3254_CLK_PLL_D_MSB_REG, 0x07},                    /* R7 Set MSB of D value D=0x0780 */
        {TI3254_PAGE_0, TI3254_CLK_PLL_D_LSB_REG, 0x80},                    /* R8 Set LSB of D value */
        {TI3254_PAGE_0, TI3254_CLK_NDAC_REG, 0x80 | 0x10},                  /* R11 NDAC divider powered on, NDAC = 16 */
        {TI3254_PAGE_0, TI3254_CLK_MDAC_REG, 0x80 | 0x03},                  /* R12 MDAC divider powered on, MDAC = 3 */
        {TI3254_PAGE_0, TI3254_DAC_OSR_MSB_REG, 0x00},                      /* R13 DOSR = 128 */
        {TI3254_PAGE_0, TI3254_DAC_OSR_LSB_REG, 0x80},                      /* R14 DOSR = 128 */
        {TI3254_PAGE_0, TI3254_CLK_NADC_REG, 0x80 | 0x10},                  /* R18 NADC divider powered on, NADC = 16 */
        {TI3254_PAGE_0, TI3254_CLK_MADC_REG, 0x80 | 0x03},                  /* R19 MADC divider powered on, MADC = 3 */
        {TI3254_PAGE_0, TI3254_ADC_OSR_REG, 0x80},                          /* R20 AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A) */
        {TI3254_PAGE_0, TI3254_BCLK_N_DIV, 0x80 | 0x0C},                    /* R30 BCLK divider powered up, val = 12 */
        {TI3254_PAGE_0, TI3254_AUDIO_IF_3_REG, 0x04},                       /* R29 Primary BCLK and Primary WCLK buffers are powered up */
        {TI3254_PAGE_0, 0x34, 0x10},        /* R52 CLKOUT on MFP5 */
        {TI3254_PAGE_0, 0x1A, 0x80 | 0x64}, /* R26 CLKOUT M powered up and divider = 100 */
        {TI3254_PAGE_0, 0x19, 0x00},        /* R25 MCLK on CDIV_CLKIN */
    };
    
    
    AudioHAL_I2CReg openScript[] =
    {
        /* Configure Analog I/O */
        {TI3254_PAGE_1, TI3254_PWR_CTRL_REG, 0x08},                         /* R1 Disabled weak connection of AVdd with DVdd */
        {TI3254_PAGE_1, TI3254_LDO_CTRL_REG, 0x08 | 0x01},                  /* R2 Analog blocks enabled, Power AVdd from LDO */
        {TI3254_PAGE_1, TI3254_ANALOG_IP_QCHRG_CTRL_REG, 0x32},             /* R71 Analog inputs power up time is 6.4 ms */
        {TI3254_PAGE_1, TI3254_REF_PWR_UP_CTRL_REG, 0x01},                  /* R123 Reference will power up in 40ms when analog blocks are powered up */
    
        /* Configure ADC */
        /* Set low-pass filter to pass everything above 1Hz (0.00045 * ADC_FS) */
        {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_N0_REG_BASE, 0x7F},         /* ADC AGC Low-pass filter Coefficient MSB N0 = 8,288,607 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N0_REG_BASE+1), 0xFF},         /* ADC AGC Low-pass filter Coefficient N0 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N0_REG_BASE+2), 0xFF},         /* ADC AGC Low-pass filter Coefficient LSB N0 */
        {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_N1_REG_BASE, 0xFF},         /* ADC AGC Low-pass filter Coefficient MSB N1 = -20,992 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N1_REG_BASE+1), 0xAE},         /* ADC AGC Low-pass filter Coefficient N1 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_N1_REG_BASE+2), 0x00},         /* ADC AGC Low-pass filter Coefficient LSB N1 */
        {TI3254_PAGE_8, TI3254_ADC_LOWPASS_COEF_D1_REG_BASE, 0x00},         /* ADC AGC Low-pass filter Coefficient MSB D1 = 512 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_D1_REG_BASE+1), 0x02},         /* ADC AGC Low-pass filter Coefficient D1 */
        {TI3254_PAGE_8, (TI3254_ADC_LOWPASS_COEF_D1_REG_BASE+2), 0x00},         /* ADC AGC Low-pass filter Coefficient LSB D1 */
        /* IIR filter cutoff at approx. 400 Hz */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE, 0x3A},  /* ADC C36 MSB Right Channel IIR N0 = 3,863,296 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE+1), 0xF3}, /* ADC C36 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N0_REG_BASE+2), 0x00}, /* ADC C36 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE, 0xF4},  /* ADC C37 MSB Right Channel IIR N1 = -736,512 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE+1), 0xC3},  /* ADC C37  */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_N1_REG_BASE+2), 0x00},  /* ADC C37 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE, 0x50},  /* ADC C38 MSB Right Channel IIR D1 = 5,262,080 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE+1), 0x4B},  /* ADC C38  */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_IIR_COEF_COEF_D1_REG_BASE+2), 0x00},  /* ADC C38 LSB */
        /* EQ filter to remove 475 Hz, 10 Hz bandwidth, -24dB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE, 0x7E},  /* ADC C39 MSB Right Channel Biquad A N0 = 8,300,800 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE+1), 0xA9},  /* ADC C39  */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N0_REG_BASE+2), 0x00},  /* ADC C39 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE, 0x81},  /* ADC C40 MSB Right Channel Biquad A N1 = -8,275,968 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE+1), 0xB8},  /* ADC C40 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N1_REG_BASE+2), 0x00},  /* ADC C40 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE, 0x7E},  /* ADC C41 MSB Right Channel Biquad A N2 = 8,289,024 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE+1), 0x7B},  /* ADC C41 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_N2_REG_BASE+2), 0x00},  /* ADC C41 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE, 0x7E},  /* ADC C42 MSB Right Channel Biquad A D1 = 8,275,968 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE+1), 0x48},  /* ADC C42 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D1_REG_BASE+2), 0x00},  /* ADC C42 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE, 0x82},  /* ADC C43 MSB Right Channel Biquad A D2 = -8,201,216 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE+1), 0xDC},  /* ADC C43 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_A_COEF_D2_REG_BASE+2), 0x00},  /* ADC C43 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE, 0x00},  /* ADC C44 MSB Right Channel Biquad A N0 = 0 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE+1), 0x00},  /* ADC C44 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N0_REG_BASE+2), 0x00},  /* ADC C44 LSB */
        {TI3254_PAGE_9, TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE, 0x40},  /* ADC C45 MSB Right Channel Biquad A N1 = 4,194,304 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE+1), 0x00},  /* ADC C45 */
        {TI3254_PAGE_9, (TI3254_ADC_RIGHT_BIQUAD_B_COEF_N1_REG_BASE+2), 0x00},  /* ADC C45 LSB */
        /* Enable filtering and set Mic bias */
        {TI3254_PAGE_8, TI3254_ADC_ADP_FILTER_CTRL_REG, 0x04},              /* Adaptive Filtering enabled for ADC */
        {TI3254_PAGE_1, TI3254_COMMON_MODE_CONTROL_REG, 0x40},              /* R10 Full Chip Common Mode = 0.75v */
        {TI3254_PAGE_1, TI3254_MICBIAS_CTRL_REG, 0x40 | 0x20 | 0x04},       /* R51 Mic bias power enabled, 2.075V, Source = LDOIN */
        {TI3254_PAGE_0, TI3254_ADC_SIG_P_BLK_CTRL_REG, 0x02},               /* R61 ADC Signal Processing Block PRB_P2 */
        {TI3254_PAGE_1, TI3254_MICBIAS_CTRL_REG, 0x40},                     /* R51 MICBIAS powered up */
    
        /* TI3254_LINE_IN */
        {TI3254_PAGE_1, TI3254_LEFT_MICPGA_P_CTRL_REG, 0x40},               /* R52 IN1L is routed to Left MICPGA with 10k resistance */
        {TI3254_PAGE_1, TI3254_LEFT_MICPGA_N_CTRL_REG, 0x40},               /* R54 CM is routed to Left MICPGA via CM1L with 10k resistance */
        {TI3254_PAGE_1, TI3254_RIGHT_MICPGA_P_CTRL_REG, 0x40},              /* R55 IN1R is routed to Right MICPGA with 10k resistance */
        {TI3254_PAGE_1, TI3254_FLOAT_IP_CTRL_REG, 0xC0},                    /* R58 IN1L input is weakly driven to common mode. Use when not routing IN1L to Left and Right MICPGA and HPL, HPR */
    
        /* Enable ADC */
        {TI3254_PAGE_1, TI3254_LEFT_MICPGA_VOL_CTRL_REG, 0x80},             /* R59 0.0dB */
        {TI3254_PAGE_1, TI3254_RIGHT_MICPGA_VOL_CTRL_REG, 0x0C},            /* R60 6.0dB with 20K impedance yields 0.0dB */
    
        {TI3254_PAGE_0, TI3254_LEFT_ADC_VOL_CTRL_REG, 0x68},                /* R83 -12dB */
        {TI3254_PAGE_0, TI3254_RIGHT_ADC_VOL_CTRL_REG, 0x68},               /* R84 -12dB */
        {TI3254_PAGE_0, TI3254_ADC_CHANNEL_SETUP_REG, 0x40},                /* R81 Right Channel ADC is powered up, Left Channel ADC is powered down */
        {TI3254_PAGE_0, TI3254_ADC_FINE_GAIN_ADJ_REG, 0x80}                 /* R82 Right ADC Channel Un-muted. Left Muted. Left and Right ADC Channel Fine Gain = 0dB */
    };
    
    
    AudioHAL_I2CReg startScript[] =
    {
        {TI3254_PAGE_0, TI3254_LEFT_DAC_VOL_CTRL_REG, 0x10},		/* R65
        {TI3254_PAGE_0, TI3254_RIGHT_DAC_VOL_CTRL_REG, 0x10},		/* R66
        {TI3254_PAGE_0, TI3254_LEFT_ADC_VOL_CTRL_REG, 0x0C},		/* R83
        {TI3254_PAGE_0, TI3254_RIGHT_ADC_VOL_CTRL_REG, 0x0C}		/* R84
    };

    I see some of your registers has multiple entries like the one below, can't you just write 0x91? I don't know the execution maybe it's ok but maybe it will take the last entry and reset the initial value. Just a thought.

    TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x80 | 0x10 | 0x01}, 

    Regards.

  • Hey,

    I looked over your script and updated ours to exactly what you have there. One register seems to have had a typo, TI3254_LDO_CTRL_REG (page 1, register 2) you have 0x81where ours is 0x08 | 0x01 or 0x09 (those registers are only being written once, with the results of that bit-wise OR). I tried out your version and with that I am able to see the PLL_CLK coming out the CLKOUT and the BCLK and WCLK. It looks like the analog block is disabled because of that change, but I can turn on the filtering and still see all the clocks, so maybe that was just getting enabled too soon?

    Not seeing data coming out yet, but at least over this hurdle!

    Thank you!