We’re trying to get a TLV320AIC3254 codec running on a pair of custom boards. Both boards have a CC2652RSIPMOTR that are acting as masters and generating the clock lines and are using the SimpleLink Audio Plugin (v3.30.0.06). One board has a microphone attached and will be sending I2S data out, the other will have that data coming in and driving line level outputs.
[microphone]--(analog)-->[TLV320A]--(I2S)-->[CC2652]--(Wireless)-->[CC2652]--(I2S)-->[TLV320A]--(analog)-->[line out]
MCLK is 12 MHz, verified with oscilloscope and when CLKOUT is configured to route that to a GPIO (MFP5) it can also be seen.
Used the AIC3254 CS application to generate appropriate PLL_CLK values for 16k sampling; R and P of 1, J.D of 8.1920, M of 3, N of 16 and AOSR and DOSR of 128.
This is the resulting clockRegs script using those values:
{TI3254_PAGE_0, TI3254_CLK_MUX_REG, 0x03}, /* PLL Clock is CODEC_CLKIN */
{TI3254_PAGE_0, TI3254_CLK_PLL_P_R_REG, 0x80 | 0x11}, /* PLL is powered up, P=1, R=1 */
{TI3254_PAGE_0, TI3254_CLK_PLL_J_REG, 0x08}, /* J=8 */
{TI3254_PAGE_0, TI3254_CLK_PLL_D_MSB_REG, 0x07}, /* D = 0780 */
{TI3254_PAGE_0, TI3254_CLK_PLL_D_LSB_REG, 0x80}, /* D = 0780 */
{TI3254_PAGE_0, TI3254_CLK_NDAC_REG, 0x80 | 0x10}, /* NDAC divider powered up, NDAC = 16 */
{TI3254_PAGE_0, TI3254_CLK_MDAC_REG, 0x80 | 0x03}, /* MDAC divider powered up, MDAC = 3 */
{TI3254_PAGE_0, TI3254_DAC_OSR_MSB_REG, 0x00}, /* DOSR = 0x0080 = 128 */
{TI3254_PAGE_0, TI3254_DAC_OSR_LSB_REG, 0x80}, /* DOSR = 0x0080 = 128 */
{TI3254_PAGE_0, TI3254_CLK_NADC_REG, 0x80 | 0x10}, /* NADC divider powered on, NADC = 16 */
{TI3254_PAGE_0, TI3254_CLK_MADC_REG, 0x80 | 0x03}, /* MADC divider powered on, MADC = 3 */
{TI3254_PAGE_0, TI3254_ADC_OSR_REG, 0x80}, /* AOSR = 128 ((Use with PRB_R1 to PRB_R6, ADC Filter Type A) */
with the addition of these:
{TI3254_PAGE_0, 0x34, 0x10},
{TI3254_PAGE_0, 0x1A, 0x80 | 0x64},
{TI3254_PAGE_0, 0x19, 0x03},
for setting up CDIV_CLKIN, CLKOUT M, and the MPF5 GPIO.
But the GPIO just stays in its high state. If that last register, 0x19, is changed to a value of 0x00 to show the MCLK then we get a 120 kHz clock on it, as expected.