Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 228 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM1681: fSCL>100kHz case

Hirokazu Takahashi
Expert 8420 points
Part Number: PCM1681

Hello Support team,

fSCL defined 100kHz as maximum at the datasheet.

If the frequency of SCL and SDA is over 100kHz, PCM1681 will ignore such a higher frequency input?

or are there any problem by setting wrong value to inside registers?

Best Regards,

Hirokazu Takahashi

  • 0
    TI__Mastermind 18750 points

    Hi,

    Our TI experts are out of office today for US holiday so please be patient as responses are delayed.

    Thank you for your patience.

    Regards,

  • 0
    TI__Mastermind 23920 points

    Hello,

    exceeding the  maximum clk frequency means violating's the max and min requirement on tr and tf and T_low and T_high. Basically in order to communicate correctly it needs 4us and 4.7us for pulse widths , plus the min time for rise and fall times. It is not that PCM1681 will ignore such a higher frequency input, exceeding the max frequency means you can not get these time requirement for these parameters and thus correct communication will not be possible.

    Regards,

    Arash