PCM1753-Q1: SPI configuration of DAC and Input/output waveform

Hi,

Our TI experts are out of office today for US holiday so please be patient as responses may be delayed.

Thank you for your patience.

Regards,

Hi,    Can you please provide the following information: 

1- The exact clk frequencies for other clks  such as  BCK, SCLK. You metioned sampling frq is 44.1kHz

2- What is the HEX reading of register 20?

3- You mentioned your data mode with LSB  first. Below is a the correct I2S format. Please make sure you follow the format correctly.

4- What are the extra glitches in your LRCLK? I see similar artifacts on BCK and data. 

5- You can set the device in HW mode and observe the behavior to eliminate the possibility of having  an issue with data in your registers

I suspect your set up is not correct. Please verify your clks , data format  and your set up in general is as expected.

Regards,

Arash

Hi Arash,

Arash Loloee said:

1- The exact clk frequencies for other clks  such as  BCK, SCLK. You metioned sampling frq is 44.1kHz

BCK is 3.08MHz, SCK is 33.8688 MHz

Arash Loloee said:

2- What is the HEX reading of register 20?

There is no provision to read the content of the register using the SPI, if it is there share it with us how can we do that? because there is no MISO pin on DAC.

Arash Loloee said:

3- You mentioned your data mode with LSB  first. Below is a the correct I2S format. Please make sure you follow the format correctly.

The attached image can't be opened, please resend it. LSB first is related to SPI master data send format. there is no co-relation between LSB first and I2S format.

Arash Loloee said:

4- What are the extra glitches in your LRCLK? I see similar artifacts on BCK and data. 

I can see those glitches in input data. So, let me clear the design for you, hdmi data goes to serializer DS90Ub949-Q1 and out from i2s pin of serializer to DAC, image is attached below.

some wavefroms without logic analyzer below.

Arash Loloee said:

5- You can set the device in HW mode and observe the behavior to eliminate the possibility of having  an issue with data in your registers

How to set device in HW mode? Though, we are using PCM1753 which is software configurable. How to reset the default setting in the device attached design?

PCM1754 is hardware controllable. 

If anything do you required regarding design, data, or waveforms, please let me know.

Regards,

Mohit

Hello Mohit,

For fs of 48kHz ( 2 channel and 32bit) BCLK=3.072MHZ , Are you sure your set up is correct for fs of 44.1kHz and number of bits you are sending? for example if you are sending 16bit with fs=44.1kHz, I would expect a BCLK of 1.41120MHz. Please check this.

PCM1753 is software control, so you can use a read command in the GUI that you are using. I usually use I2C master in PPC myself for writing and reading registers. If you are using the GUI that user's guide is talking about, then it has some screen shot of the default registers settings and the one that you write to it. Please refer to  chapter 2 in SLEU104–March 2009

The figure that I sent you is from datasheet (Figure 23. Audio Data Input Formats,) and it indicates the I2S format expects MSB to be the first bit. In a perfect condition, if you send the bits the other way around you will not get what you expect but I think I would concentrate on the clk set up first before moving on.

Also make sure you send clean input and clks to the DAC, without any clitchés as those extra H and Lo in the clks can mess things up. 

Regards,

Arash

Hello Arash, 

Can we have a meeting to clear some things? I am sending you the friend request so that I can share my personal e-mail address to setup the meeting.

Thanks & Regards,
Vivek Karna

No problem.

Hi Arash,

It is verified that serializer is sending wrong output to DAC. It is visible in waveform that serializer is sending 32-bit data clock (2.822 Mhz) all the time when we give 16-bit and 24-bit data from HDMI. 

Would you please support us on serializer part DS90Ub949-Q1?

Thanks and regards,

Mohit

Hi Mohit. So the issue as I was suspected  was the wrong clk to the DAC. For DS90Ub949-Q1 support you need to create a new thread as I am not familiar with DS90Ub949-Q1. 

So I think I can close this thread at this moment.

Regards,

Arash

Hello Arash,

We are not sure if the DS-949 device is the main reason behind this issue or not. But, we are finding this thing.

Meanwhile, can you please tell me how to program the DAC using SPI or I2C? Because, whenever I am using the SPI master device, the very first time when the SPI clock is going to the CLK pin of the DAC, the output is gone. Can you tell me the reason behind this? Though, the DAC programming operation shouldn't be in sync with the I2S input data of DAC, so why during programming, is DAC output gone?

Do I have to follow some particular timing sequence while doing software operations with the DAC?



 The above capture is taken from the DAC datasheet, so by default, the DAC is set to 44.1 kHz, so I am sending the data to the DAC at 100kbps to match the timing sequence. Am I right?

Please share with me how to program the DAC, is there anyway, I can read the DAC registers?

Because, if I am going to use an I2C master device, the I2C master will wait for the ACK from DAC, but as per my knowledge, the DAC wouldn't respond with the ACK, that's why the SPI method is used with the DAC. Please tell me that I am thinking in the right way.

Thank you,
Vivek Karna

Hello Vivek,

 Since it  uses ML, MC and MD  pin  to program , not I2C,   we can't use I2C master. I originally thought it supports SPI and I2C as well.

If you are using the device in the default configuration, the PCM1753 does not require any programming. 

Please refer to section 8.5.1 Software Control (PCM1753/55) and read through the steps for writing to registers using these 3 pins.  All write operations for the serial control port use 16-bit data words that is shown in figure 26 and 27.  As long as you stay within the limits of interface control shown in 7.8, you  should be okay. 

Unfortunately it is not possible to read back the data you  write for this device as it doesn't have the MISO feature!!  Here is another post that you can go through with some common questions and answers.

https://e2e.ti.com/support/audio-group/audio/f/audio-forum/678901/pcm1753-mono-dac-configuration

Regards,

Arash

Hi Arash,

As per DAC datasheet, it supports 2 channels left and right of 32 bits(total 64 bits) with data 24 bit left justified. Since the sampling rate is 44.1KHz (64x44.1) will result in I2S(BCK) 2.84MHz.

We tried with different clock input to SCK pin of DAC 5.6448, 8.4672, 11.2896 MHz. 

It looks the I2s input to the DAC follows the requirement based on sampling (44.1KHz), word size (2x32=64), and 24-bit left justified but still DAC output audio is distorted or not clear.

could you share/confirm for us that the default format is 24-bit left justified or something else right justified/ I2S?

Regards,

Mohit

Hi Mohit,

Yes, the default is 24bit length,  left justified.

The 2 plots above are not  related to each other, correct?  Because  the colors are different for each waveforms.

I would make sure that clks are correct, specially BCK .  I can not see it clearly in your last plot. And the first set of waveforms look strange (for example the Low side of LRCLK seems ok but high side is not) 

If possible use AP to generate the clks and select the formats using AP . 

Regards,

Arash

Hi Arash,

Arash Loloee said:

Yes, the default is 24bit length,  left justified.

Thank you for confirming this.

Arash Loloee said:

The 2 plots above are not  related to each other, correct?  Because  the colors are different for each waveforms.

The two plots are the same only difference is, the upper one is taken from logic analyzer and the lower is taken from scope.

Arash Loloee said:

I would make sure that clks are correct, specially BCK .  I can not see it clearly in your last plot. And the first set of waveforms look strange (for example the Low side of LRCLK seems ok but high side is not) 

We will share the waveform generator clock plots which would make it clear in the case of BCK. It seems that LRCK waveform's higher side pulse has distortions.

Arash Loloee said:

If possible use AP to generate the clks and select the formats using AP .

What is AP and its procedure? do you mean waveform generator or else? 

Regards,

Mohit

Hi Arash,

Would you send us the correct LRCK and BCK waveform? I have tried using waveform generator clocks but result is same.

Hi,

Out TI experts are out office today for US holiday so please be patient as responses are delayed.

Hi Mohit,

In Audio we usually use Audio Precision (AP) to generate clks, signal, analyze and so on. It is probably one of the most popular tools(if not the most).

AP  has several windows: for generating digital signal, analog signal, analyzing the receiving Digital or Analog signal, fft and more. I am showing only the CLK generator window from the AP GUI.

Here I can choose the number of channels, Frame clk, (LRCLK) and # of bits for each channel and .. . Once I change anything in this GUI, I can see the resulted clk due to my changes and thus I can verify with scope if I see what I expect , for  example my  Bit clk is 3.072MHz and I can verify it with scope.

the waveforms generated by AP from  the above set up   is the following:

Regards,

Arash

Hi Arash,

Could you share your configuration or schematics of PCM1753? I need to confirm that how you use ML, MC, MD pins on DAC in setting up 24 bit length data, left justified.

Regards,

Mohit

Hello,

You can find the schematic for the EVM in  SLEU104–March 2009  (page20-21) .

Regards,

Arash