The datasheet states that poepr filtering for GVDD and AVDD shall be provided with a 3R3 and 1uF. Howver it shows the series resistor in th GVDD (pin1), other than in the EMV module. I believe that GVDD is for teh gate drive and shall be conncted dirrectly to 5V while the analog AVDD shall be filtered. The figures 10.1 nd figures 10.6 are incorrect in this case.