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TLV320DAC32: Audible Hiss/Static

Jimy Pesin
Prodigy 10 points
Part Number: TLV320DAC32


We have implemented the TLV320DAC32IRHBR in our audio pathway. Whenever we are about to play audio files, we hear a distinct hissing noise prior to audio being played. In previous designs, we used a different codec and we did not have any hissing when playing audio so we would like to understand if it is related to how we configured the codec or the interface to the amplifier. 

  • 0
    TI__Guru** 111175 points

    Hi Jimy,

    Can you please share the register configuration you're using? Your initialization script or a register dump after the initialization would be OK.
    Please also share the input clock frequencies from the host, MCLK, BCLK and WCLK.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0
    Prodigy 30 points

    Ivan -

    Thank you for your help. I have copied our register settings from the code. We configure the codec only once at initialization. The registers are not changed while the device is operating. Please let me know if there is anything you would like me to try on our end.

    Sincerely,

    Scott Ellerthorpe

    Principle Firmware Engineer

    Clock Frequencies
    MCLK 12 MHz
    BCLK 20 MHz

    Fsref = 48 kHz

    Register Settings (all others left at default)

    tlv320_init_array1[ 0] = TLV320_REG0_PAGE_SEL; // starting address for auto increment
    tlv320_init_array1[ 1] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_PAGE_SEL 0x00 //0
    tlv320_init_array1[ 2] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_SW_RESET 0x01 //1
    tlv320_init_array1[ 3] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_DAC_SAMP_RATE 0x02 //2
    tlv320_init_array1[ 4] = 0x11; // regValue: 0b00010000 0x10 regName: TLV320_REG0_PLL_PROG_A 0x03 //3
    tlv320_init_array1[ 5] = 0x20; // regValue: 0b00000100 0x04 regName: TLV320_REG0_PLL_PROG_B 0x04 //4
    tlv320_init_array1[ 6] = 0x1E; // regValue: 0b00011110 0x1E regName: TLV320_REG0_PLL_PROG_C 0x05 //5
    tlv320_init_array1[ 7] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_PLL_PROG_D 0x06 //6
    tlv320_init_array1[ 8] = 0x08; // regValue: 0b00011000 0x18 regName: TLV320_REG0_DAC_DATAPATH 0x07 //7
    tlv320_init_array1[ 9] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_AUDIO_SDI_A 0x08 //8
    tlv320_init_array1[10] = 0x00; // regValue: 0b00110000 0x30 regName: TLV320_REG0_AUDIO_SDI_B 0x09 //9
    tlv320_init_array1[11] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_AUDIO_SDI_C 0x0A //10
    tlv320_init_array1[12] = 0x01; // regValue: 0b00000001 0x01 regName: TLV320_REG0_AUDIO_DAC_OVRFL 0x0B //11
    tlv320_init_array1[13] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_AUDIO_DAC_FILTER 0x0C //12
    tlv320_init_array1[14] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_BUTTON_DETECT_A 0x0D //13
    tlv320_init_array1[15] = 0xC0; // regValue: 0x11000000 0xC0 regName: TLV320_REG0_BUTTON_DETECT_B 0x0E //14
    tlv320_init_array1[16] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x0F //15
    tlv320_init_array1[17] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x10 //16
    tlv320_init_array1[18] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x11 //17
    tlv320_init_array1[19] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x12 //18
    tlv320_init_array1[20] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x13 //19
    tlv320_init_array1[21] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x14 //20
    tlv320_init_array1[22] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x15 //21
    tlv320_init_array1[23] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x16 //22
    tlv320_init_array1[24] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x17 //23
    tlv320_init_array1[25] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x18 //24
    tlv320_init_array1[26] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_MICBIAS 0x19 //25
    tlv320_init_array1[27] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x1A //26
    tlv320_init_array1[28] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x1B //27
    tlv320_init_array1[29] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x1C //28
    tlv320_init_array1[30] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x1D //29
    tlv320_init_array1[31] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x1E //30
    tlv320_init_array1[32] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x1F //31
    tlv320_init_array1[33] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x20 //32
    tlv320_init_array1[34] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x21 //33
    tlv320_init_array1[35] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x22 //34
    tlv320_init_array1[36] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x23 //35
    tlv320_init_array1[37] = 0x00; // regValue: 0x00000000 0x00 regName: RESERVED 0x24 //36
    tlv320_init_array1[38] = 0x80; // regValue: 0b10000000 0x80 regName: TLV320_REG0_DAC_OUTPUT_DRV 0x25 //37
    tlv320_init_array1[39] = 0x02; // regValue: 0b00000010 0x02 regName: TLV320_REG0_HIPWR_OUTPUT_DRV 0x26 //38

    tlv320_init_array2[ 0] = TLV320_REG0_HIPWR_OUTPUT; // starting address for auto increment
    tlv320_init_array2[ 1] = 0x80; // regValue: 0b00000000 0x00 regName: TLV320_REG0_HIPWR_OUTPUT 0x28 //40
    tlv320_init_array2[ 2] = 0x80; // regValue: 0b10000000 0x80 regName: TLV320_REG0_DAC_OUTPUT_SW 0x29 //41
    tlv320_init_array2[ 3] = 0x34; // regValue: 0b00110100 0x34 regName: TLV320_REG0_OUTPUT_DRV_POP 0x2A //42
    tlv320_init_array2[ 4] = 0x00; // regValue: 0b00000000 0x00 regName: TLV320_REG0_VOL_DACL 0x2B //43 VOLUME
    tlv320_init_array2[ 5] = 0xFF; // regValue: 0b11111111 0xFF regName: TLV320_REG0_VOL_DACR 0x2C //44

    tlv320_init_array3[ 0] = TLV320_REG0_VOL_DACL_HPLOUT; // starting address for single write
    tlv320_init_array3[ 1] = 0x80; // regValue: 0b10000000 0x80 regName: TLV320_REG0_VOL_DACL_HPLOUT 0x2F //47

    tlv320_init_array4[ 0] = TLV320_REG0_HPLOUT_OUTPUT_LEVEL; // starting address for single write
    tlv320_init_array4[ 1] = 0x2D; // regValue: 0b00101101 0x2D regName: TLV320_REG0_HPLOUT_OUTPUT_LEVEL 0x33 //51 VOLUME

    tlv320_init_array6[ 0] = TLV320_REG0_ADDITIONAL_B; // starting address for auto increment
    tlv320_init_array6[ 1] = 0x01; // regValue: 0b00000001 0x01 regName: TLV320_REG0_ADDITIONAL_B 0x65 //101
    tlv320_init_array6[ 2] = 0x08; // regValue: 0b10001000 0x88 regName: TLV320_REG0_CLOCK_GEN 0x66 //102

  • 0 in reply to Scott Ellerthorpe
    TI__Guru** 111175 points

    Hi Scott,

    I'll check this and get back to you with further comments within a couple of days.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0
    Prodigy 30 points

    Ivan -

    Have you been able to test our configuration yet?

    Sincerely,

    Scott Ellerthorpe

    Principle Firmware Engineer

  • 0 in reply to Scott Ellerthorpe
    TI__Guru** 111175 points

    Hi Scott,

    I lost track of this one and haven't tested yet, I'll add some comments by tomorrow end of the day.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    TI__Guru** 111175 points

    Hi Scott,

    I've been dealing with some troubles with this old evaluation module but got it working for now. I used your script and got output signals, left channel is higher amplitude though.

    However, this test was using some default I2S-48kHz configuration from the host (Audio Precision APx 500), then I noticed you mentioned MCLK 12 MHz
    BCLK 20 MHz. Could you please double check if these are the correct clock frequencies? Usually at least BCLK is a multiple of WCLK (48kHz) as it is given by BCLK = Fs * (Number of Channels) * (Bits per channel).

    Regarding the difference in amplitude between the channels, I'll give further comments once I completely analyze your register configuration script.

    Best regards,
    -Ivan Salazar
    Applications Engineer

  • 0 in reply to Ivan Salazar
    Prodigy 30 points

    I talked with the hardware engineer. MCLK=12,289,966 Hz, WCLK=48 kHz, BLCK=3072 kHz (32 bit data). Apologies for the confusion. We are only using the left channel.

    Sincerely,

    Scott Ellerthorpe

  • 0 in reply to Scott Ellerthorpe
    TI__Mastermind 48515 points

    Thanks for the update Scott,

    Ivan is out of office for the next week so another member of the team will be supporting you until he returns if necessary.

    Thanks,

    Jeff McPherson

  • 0 in reply to Scott Ellerthorpe
    TI__Guru** 111175 points

    Hi Scott,

    It's been some time since last communication, can you please let me know if there's any update from your side? Is the hissing noise still perceived on your test? Are you testing only on 1 device or several count?

    From your last comment, and my previous test, it seems your configuration should be OK. It shows that you're using the same clock settings as I did with APx500, I used your script and the fact that I only got left channel signal is OK based on your description as well.

    Can you confirm if the clocks are present all the time from when the device is initialized to the time audio is played? FYI the clocks should not be interrupted once the DAC is initialized through I2C.

    Best regards,
    -Ivan Salazar
    Applications Engineer