TLV320ADC3101EVM-K: TLV320ADC3101EVM-K

Can you please reduce the input to 100mvpp and Check if you observe a sine wave at the output?

Are you using the I2C settings given on page 80 of datasheet?

https://www.ti.com/lit/ds/symlink/tlv320adc3101.pdf?ts=1683563775249&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV320ADC3101

Hi Sanjay,

ok, with 100mV p-p we see a sine wave output without any clipping but data read back from DAC is approximate 5V p-p.

We are using only through GUI, the setting mentioned on page 80 are possible to be done with GUI?

What is the value of PGA Gain? Page 1 Register 59 and 60 ? 

Hi Sanjay,

Please find below screenshot of gain settings on GUI.

Let me know for more inputs.

Please try setting PGA Gain to 0db

PGA gain is set to 0, please check attachment.

Now, we see output of 3 Vp-p for input of 1V p-p for 1KHz frequency.

0.7Vrms correponds to full scale digital Value.The ADC must be giving Full scale value. Please check what voltage your DAC Delivers when receiving Full scale input

Hi Sanjay,

With 0.7Vrms, we see almost 6V p-p at DAC output. Please find attached screenshot.

You need to check from DAC Specifications the below:

What is the output voltage that DAC makes when receioving full scale digital input?

Hi,

There is no gain added from DAC as we are able to read proper input signal from other Audio ADC on the same DAC.

Is there any clock settings we need to make as we are not able to read the correct signal frequency.

I am sorry i am not clear. 

Are you not able to detect input signal frequency?i can see you have put some plots

Yes, i can see sine signal but not able to read back the input signal frequency provided to ADC.

I see you have a timescale in your plot. By using the time elapsed between 2 peaks you should be able to determine the frequency

Page 80 of the datasheet provides I2C Settings.These can be used to setup the chip 

https://www.ti.com/lit/ds/symlink/tlv320adc3101.pdf?ts=1683790069668&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTLV320ADC3101

Hi Sanjay,

I have some updates on this:

1) I am currently loading script of "Line in stereo recording" and I checked the page 80 sequence of I2S settings and the loaded script from GUI covers the things specified in page 80.

2) Now, by making "Single- Ended IN1L(P)" to (-6dB) and ADC gain L to (-4dB) [Below attached screenshots of these], I am able to see the correct output in terms of amplitude till 2.2V peak.

Below 2 are concerns now:

1) The output amplitude is linear till 2.2Vp but output will not go beyond 2.2 Vp even though input is increased.

2) The Output frequency is always multiplied by 4x of input frequency. For Ex (Output is 4KHz if input is 1KHz).

Let me know how these can be corrected.

PS: I have given 1V peak, 1KHz single ended signal to J6 of EVM.

Please check the sampling Rate to the DAC. It may be some issue there

HI Sanjay,

Right, by reducing the sampling rate on DAC fixed the frequency part of it.

Do you have any comments for "The output amplitude is linear till 2.2Vp but output will not go beyond 2.2 Vp even though input is increased."

You must have reached the maximum level for full scale data. Please send me a plot of what you see

Hi,

Please find below screenshot:

We have DAC specifications, I2S clock frequency 2.8224MHZ and sampling Frequency 44.1KHz. The output signal is fine till 4KHz but after the 5KHz the sine wave is disturbed. I have attached screenshot of signal at 10Khz output  read from DAC.

Try to make the timings to the ADC and DAC the same. If the ADC is setup at 48Khz (Fs) then the DAC Also should have the same timing.

DAC outputs sometimes have RC Low pass filters at output. Please check the cutoff frequency for the filter

The sampling frequency is same at ADC and DAC i.e. 44.1KHz. There is no filtering at DAC as we are able to read till 20KHz properly from other ADC.

Not sure if there is any settings on TLV320 Eval board which needs to be done.

To begin with check the input signal waveform on the Input pins of the ADC.

Please check from 1k to 10k.

Are you giving the below timings ?

MCLK = 11.2896 MHz, # BCLK = 2.8224 MHz, WCLK = 44.1 kHz

is the sample code the exact as the datasheet?

You have to match the settings of ADC and DAC. Are you using I2S 16 bits for both?

Yes, the settings are same as datasheet MCLK = 11.2896 MHz, # BCLK = 2.8224 MHz, WCLK = 44.1 kHz.
I see the signal is disturbed from 4KHz.

Is the signal at input pin is disturbed from 4K onwards then there is some issue with the input circuit.

Can you please describe the connections to the input pin?