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PCM1690: External Reset

Part Number: PCM1690

Hello,

PCM1690's data sheet describes in the section 7.3.5 Reset Operation, "Figure 24 shows a timing diagram...If RST goes from high to low under synchronization among SCKI, BCK, and LRCK, the internal reset is asserted, ..." What if RST goes from high to low when these audio clocks are NOT synchronized? In this case, won't the internal reset be asserted? I'd like to confirm whether the internal reset is asserted or not when any of the audio clocks are not provided.

Best regards,
Shinichi Yokota

  • Hello Shinichi ,

    Yes, If external reset toggles high to low ( sending a request for RESET or initialization) but  clks are not correct , internal initialization and reset is not triggered. Once clks are synchronized and ready, after 3846 SCLK the reset happens- ( assuming by then external reset is already back to high. If external Reset is still low, it waits until it goes High, then after 3846 clk , DAC starts again. 

    Regards,

    Arash

  • Arash,

    ...but  clks are not correct ...

    Could you elaborate on that? I'm afraid I cannot image what exactly the "correct" means. Is it the state where all the SCKI, BCK, and LRCK clocks are synchronized? Or, is it OK if just the SCKI clock is provided?

    What I'd like to know is, "How long do the SCKI, BCK, and LRCK clocks need to be kept synchronized after the RST signal is asserted?" I cannot figure it out from the data sheet.

    Best regards,
    Shinichi Yokota

  • If external RST goes from high to low under synchronization among SCKI, BCK, and LRCK ( which i referred to it as clocks are correct ) , the internal reset will be  asserted immediately and thus all registers and memory are reset. Once RST is toggled back high, after 3846 x SCKI the internal reset is released.

    Regards,

    Arash