I'm designing a system that will use four TPA3220s in PBTL mode. I'm planning to configure them as slaves and supply an external clock on the OSCx pins, so I can fine tune the PWM frequency and have some insurance against EMI surprises.
I understand that the IC creates its PWM clock by dividing the OSCx clock by six. The August 2018 data sheet section 9.3.2 shows how multiple ICs can be connected to offset their PWM switching times and minimise the demand on the system power supply; but it uses one IC as a master and the others as slaves, and offsets the switching by 30 degrees. It implies that all the ICs must have a common reset signal to achieve this synchronisation.
I'd like to do a similar thing in my application, but offsetting each IC's PWM by 22.5 degrees since there are four of them. I have no problem generating offset clocks, but these clocks will be at the OSCx frequency of 3.6MHz (nominal) and not the IC's PWM frequency. The divide-by-six seems to be entirely internal to the IC so I see no way of forcing, or even knowing, the timing of an IC's PWM clock with repsect to its OSCx clock. (Other than sampling the PWM outputs, which is impractical.)
Is there some way I can make this work? Perhaps with careful control of when the reset signal is negated on each IC? Is there any more detailed documentation on how the oscillator works?
