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TLV320ADC6140: How to config the route for TLV320ADC6140 on NXP's iMX6u with Linux4.1.15?

Part Number: TLV320ADC6140

Dear all,

Now we are trying to use TLV320ADC6140 on NXP's iMX6u, and the OS is Linux 4.1.15.

For the hardware, we connect 4 vibration sensors to the tlv320adc6140, which have the same analog differential signal output as the mic. And the tlv320 will sample the signal and we will finally use the alsa interface to collect the data.

For the software, now the tlv320adc6140's codec driver has been successfully ported according to the official driver, and I also write a machine driver to connect the platform and codec. Now the sound card can be registered successfully. But I am still confused with the route configuration I connected.

The following is my route configuration now:

{"MIC1P", NULL, "MIC0"} //Use mic0 as my first vibration sensor
{"MIC1M", NULL, "MIC0"}
{"MIC2P", NULL, "MIC1"}
{"MIC2M", NULL, "MIC1"}
{"MIC3P", NULL, "MIC2"}
{"MIC3M", NULL, "MIC2"}
{"MIC4P", NULL, "MIC3"}
{"MIC4M", NULL, "MIC3"}
{"Capture", NULL, "CH1_ADC"}
{"Capture", NULL, "CH2_ADC"}
{"Capture", NULL, "CH3_ADC"}
{"Capture", NULL, "CH4_ADC"}
{"CPU-Capture", NULL, "Capture"}

Am I configed correctly? I am lack of this audio experience.

If you need more information, please let me know.

Chad

  • Thanks for bringing this to our attention, expect a response in the next 48 business hours. 

    Regards,

    Ore.

  • any news?

    Now I am trying to capture a wav audio stream, but I only can measure the BCLK, no data at all. Do you have any idea?

    Chad

  • Hey Chad, 

    Are you saying you are trying to figure out how to set up the input terminals for your application ? If so please share a schematic.

    Regards, 

    Ore. 

  • Hi Ore,

    Yes, this is the schematic:

    About iepe4, it is a conversion module, use EDDY_IN4 and TMP_IN4 as input. And for R504, R505, and R506, they are not used. If it is not enough, please let me know.

    Thanks

    Chad

  • Hey Chad, 

    Thanks for the feedback. Expect a response end of day tomorrow. 

    Regards,

    Ore. 

  • Hey Chad,

    A couple things to note: 

    • pull the SDA and SCL pins to IOVDD
    • pay attention to the i2c address settings:                                                                                  

    Regards,

    Ore.  

  • Hi Ore,

    Thanks for your note. Now my IIC works fine. I can read and write register successfully.

    The latest updates: when I am trying to use "arecord -D hw:0,0 -f cd test.wav" to capture, I can measure BCLK=1.41mHz, and FSYNC=44.1kHz, but no data at all.

    What do you think I should check?

    Thanks

    Chad

  • Hey Chad,

    Before we go on, what are you using to configure your ADC? 

    The best way to configure your ADC is using pure path console 3(ppc3) and you can make a request here: 

    www.ti.com/.../PUREPATHCONSOLE

    Regards,

    Ore. 

  • Hi Ore,

    Thanks for your reply.

    But I do not think ppc3 will do much for me. Now I am working on embedded linux system. And now my problem is the devices does not work.  But PPC3 seems to be designed for sound optimization.

    We have used tlv320adc6140 on stm32, so as long as the chip works, we have relevant experience in the later optimization.

    About config the ADC, I add an interface to the driver which allows to read and write the registers.

    Now my registers are as follows:

    0x00=0x00
    0x01=0x00
    0x02=0x81
    0x05=0x05
    0x07=0x00
    0x08=0x00
    0x09=0x00
    0x0B=0x00
    0x0C=0x01
    0x0D=0x02
    0x0E=0x03
    0x0F=0x04
    0x10=0x05
    0x11=0x06
    0x12=0x07
    0x13=0x02
    0x14=0x48
    0x15=0x44
    0x16=0x10
    0x1F=0x40
    0x20=0x00
    0x21=0x22
    0x22=0x00
    0x23=0x00
    0x24=0x00
    0x25=0x00
    0x29=0x00
    0x2A=0x00
    0x2B=0x00
    0x2C=0x00
    0x2F=0x00
    0x32=0x00
    0x33=0xFF
    0x36=0x00
    0x3B=0x00
    0x3C=0x00
    0x3D=0x00
    0x3E=0xC9
    0x3F=0x80
    0x40=0x00
    0x41=0x00
    0x42=0x00
    0x43=0xC9
    0x44=0x80
    0x45=0x00
    0x46=0x00
    0x47=0x00
    0x48=0xC9
    0x49=0x80
    0x4A=0x00
    0x4B=0x00
    0x4C=0x00
    0x4D=0xC9
    0x4E=0x80
    0x4F=0x00
    0x52=0xC9
    0x53=0x80
    0x54=0x00
    0x57=0xC9
    0x58=0x80
    0x59=0x00
    0x5C=0xC9
    0x5D=0x80
    0x5E=0x00
    0x61=0xC9
    0x62=0x80
    0x63=0x00
    0x6B=0x01
    0x6C=0x40
    0x6D=0x7B
    0x70=0xE7
    0x73=0xF0
    0x74=0xF0
    0x75=0xE0
    0x76=0xF0
    0x77=0xE0

    I checked all of them, looks like they are normals. So it is very strange.

    Thanks

    Chad

  • Thanks for the feedback Chad. Expect a response in 48hrs. 

    Regards,

    Ore.

  • Hi Ore,

    I made some progress~

    Now I can receive the data, but could not support 4 channels, only 3 channnels.

    I find that the problem may be the number of clocks.

    As figures in datasheet:

    The cpu send out the FSYNC and BCLK with no idle BCLK Cycles, but our TLV320ADC6140 send out the Data on SDOUT with standard protocol timing.

    So do you know how to config the idle BCLK Cycles? I did not find any information about it.

    Thanks

    Chad

  • Hey chad, 

    To confirm if ch4 is actual idle, try moving ch4 to slot 0. Disable ch1-3 using this register: 

    then leaving ch4 on, move it to slot 0 using this register:

    Let us know what you observe.

    Regards,

    Ore. 

  • Hey Ore,

    Thanks for your suggestion~

    Yes, I can get the ch4's data. After it started sampling, I write (0x73,0x10), (0x0E,0x00) and (0x74,0x10), then I get the following waves:

    I think it is normal.

    Thanks

    Chad

  • Hey Chad,

    It looks like you are using 16bits/ch for your configuration based off your reg 0x07. You need to follow this formula to get the accurate BCK for your ASI bus: 

    BCK= fs*#ch*bits/ch. 

    In your case, your BCK should be 

    BCK=44.1k * 16 * 4 = 2.83MHz not 1.4MHz.

    Once that is implemented, let us know if the 4 channels dont work

    Regards,

    Ore.

  • Hi Ore,

    Sorry, forget to tell you.

    Yes, you are right. Now my BCK is 2.83MHz, not 1.4MHz. At first I could not get any data, so I used 1.4MHz to see if single or dual channels can work.

    Current situation:

    Regs:

    0x00=0x00
    0x01=0x00
    0x02=0x81
    0x05=0x05
    0x07=0x40
    0x08=0x00
    0x09=0x00
    0x0B=0x00
    0x0C=0x20
    0x0D=0x21
    0x0E=0x22
    0x0F=0x04
    0x10=0x05
    0x11=0x06
    0x12=0x07
    0x13=0x02
    0x14=0x48
    0x15=0x44
    0x16=0x10
    0x1F=0x40
    0x20=0x00
    0x21=0x22
    0x22=0x00
    0x23=0x00
    0x24=0x00
    0x25=0x00
    0x29=0x00
    0x2A=0x00
    0x2B=0x00
    0x2C=0x00
    0x2F=0x00
    0x32=0x00
    0x33=0xFF
    0x36=0x00
    0x3B=0x00
    0x3C=0x00
    0x3D=0x00
    0x3E=0xC9
    0x3F=0x80
    0x40=0x00
    0x41=0x00
    0x42=0x00
    0x43=0xC9
    0x44=0x80
    0x45=0x00
    0x46=0x00
    0x47=0x00
    0x48=0xC9
    0x49=0x80
    0x4A=0x00
    0x4B=0x00
    0x4C=0x00
    0x4D=0xC9
    0x4E=0x80
    0x4F=0x00
    0x52=0xC9
    0x53=0x80
    0x54=0x00
    0x57=0xC9
    0x58=0x80
    0x59=0x00
    0x5C=0xC9
    0x5D=0x80
    0x5E=0x00
    0x61=0xC9
    0x62=0x80
    0x63=0x00
    0x6B=0x01
    0x6C=0x40
    0x6D=0x7B
    0x70=0xE7
    0x73=0xF0
    0x74=0xF0
    0x75=0xE0
    0x76=0xF0
    0x77=0xE0

    This register list supports 4 channels,the waveforms I measured were very messy.

    but if I write (0x74,0xE0) to disable channel 4, then I can get a right waveforms like this:

    About only test channel 4, like we talked before, it also works fine.

    Thanks

    Chad

  • Explain the waveform. The blue is bck, correct? What is the yellow and pink? 

    And according to reg 0x07, you are in i2s mode which supports only 2 channels. Use tdm mode that supports multiple channels. 

  • Hi Ore,

    Thanks, I know where I made a mistake now.

    I have seen a blog that the number of slots in each channel can be different for IIS mode, and the waveform can be symmetrical, so I mistakenly think that FSYNC is OK.

    I will try to use TDM mode, if there is other problem, I will ask a now question. For this question, I will close.

    Thanks again~

    Chad