TAS2560: Tas2560

Hi Nadeem,

Let me add some background information on digital input audio amplifiers: Usually the digital audio data comes at least in stereo (I2S, RJF, LJF) and if more than 2 channels are required, TDM is used to transmit multiple audio channel data sets. When the application requires only 1 audio channel, it usually uses left channel (first set of data) leaving the right channel (or all other data slots) empty. Alternatively, the audio amplifier can mix both left and right channels together which is usually called mono-mix.

 Based on this, would you be able to append an empty set of 16bits from your host controller to match the conventional audio data transfer? Most likely the audio is all scrambled because the device is only playing half of the audio samples.

Regarding the burst, this is just a command to send several consecutive register data, instead of addressing each register individually in a sequence. The burst command itself depends on the controller, but from I2C protocol perspective this is known as "repeated start".

Best regards,
-Ivan Salazar
Applications Engineer

Dea Ivan,

Thanks for your reply.

I will try what you have mentioned and see what happens.

Nadeem,

Let us know how the test goes or if there are any further questions.

Best regards,
-Ivan Salazar
Applications Engineer

Dear Ivan,

Now coming to TAS2560 Configurations, we used the Pure Console to generated the CFG

//48khz bclk 1.536 mhz
cfg_reg registers[] = {
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x07, 0x41 },
{ CFG_META_DELAY, 0x10 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x07, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x01, 0x01 },
{ CFG_META_DELAY, 0x10 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
// Specify the clock (MCLK/BCLK)
{ 0x0f, 0x01 },
// PLL P
{ 0x0f, 0x01 },
// PLL J
{ 0x10, 0x20 },
// PLL D - MSB 6 bits
{ 0x11, 0x00 },
// PLL D - LSB 8 bits
{ 0x12, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x00 },
//decimation and interpolation
{ 0x0d, 0x08 },
{ 0x0e, 0x10 },
//clock error detection
{ 0x50, 0x31 },
{ 0x04, 0x5f },
{ 0x15, 0x02 },
{ 0x09, 0x83 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0xfd },
{ 0x36, 0xc6 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x08, 0x01 },
{ 0x36, 0x32 },
{ 0x22, 0x3f },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x49, 0x0c },
{ 0x3c, 0x33 },
{ 0x02, 0x02 },
{ 0x07, 0x41 },
{ CFG_META_DELAY, 0x10 },
{ 0x00, 0x32 },
{ 0x28, 0x7f },
{ 0x29, 0xfb },
{ 0x2a, 0xb5 },
{ 0x2b, 0x00 },
{ 0x2c, 0x80 },
{ 0x2d, 0x04 },
{ 0x2e, 0x4c },
{ 0x2f, 0x00 },
{ 0x30, 0x7f },
{ 0x31, 0xf7 },
{ 0x32, 0x6a },
{ 0x33, 0x00 },
{ 0x1c, 0x7f },
{ 0x1d, 0xff },
{ 0x1e, 0xff },
{ 0x1f, 0xff },
{ 0x20, 0x00 },
{ 0x21, 0x00 },
{ 0x22, 0x00 },
{ 0x23, 0x00 },
{ 0x24, 0x00 },
{ 0x25, 0x00 },
{ 0x26, 0x00 },
{ 0x27, 0x00 },
{ 0x00, 0x33 },
{ 0x18, 0x06 },
{ 0x19, 0x66 },
{ 0x1a, 0x66 },
{ 0x1b, 0x66 },
{ 0x00, 0x34 },
{ 0x34, 0x3a },
{ 0x35, 0x46 },
{ 0x36, 0x74 },
{ 0x37, 0x00 },
{ 0x38, 0x22 },
{ 0x39, 0xf3 },
{ 0x3a, 0x07 },
{ 0x3b, 0x00 },
{ 0x3c, 0x80 },
{ 0x3d, 0x77 },
{ 0x3e, 0x61 },
{ 0x3f, 0x00 },
{ 0x40, 0x22 },
{ 0x41, 0xa7 },
{ 0x42, 0xcc },
{ 0x43, 0x00 },
{ 0x44, 0x3a },
{ 0x45, 0x0c },
{ 0x46, 0x93 },
{ 0x47, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x33 },
{ 0x10, 0x75 },
{ 0x11, 0xc2 },
{ 0x12, 0x8e },
{ 0x13, 0x00 },
{ 0x14, 0x6e },
{ 0x15, 0x14 },
{ 0x16, 0x79 },
{ 0x17, 0x00 },
{ 0x20, 0x1e },
{ 0x21, 0x00 },
{ 0x22, 0x00 },
{ 0x23, 0x00 },
{ 0x24, 0x21 },
{ 0x25, 0x3d },
{ 0x26, 0x71 },
{ 0x27, 0x00 },
{ 0x28, 0x24 },
{ 0x29, 0x7a },
{ 0x2a, 0xe1 },
{ 0x2b, 0x00 },
{ 0x2c, 0x27 },
{ 0x2d, 0xb8 },
{ 0x2e, 0x52 },
{ 0x2f, 0x00 },
{ 0x30, 0x2a },
{ 0x31, 0xf5 },
{ 0x32, 0xc3 },
{ 0x33, 0x00 },
{ 0x34, 0x2e },
{ 0x35, 0x33 },
{ 0x36, 0x33 },
{ 0x37, 0x00 },
{ 0x38, 0x31 },
{ 0x39, 0x70 },
{ 0x3a, 0xa4 },
{ 0x3b, 0x00 },
{ 0x3c, 0x34 },
{ 0x3d, 0xae },
{ 0x3e, 0x14 },
{ 0x3f, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x32 },
{ 0x3c, 0x3d },
{ 0x3d, 0x99 },
{ 0x3e, 0x9a },
{ 0x3f, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x32 },
{ 0x40, 0x30 },
{ 0x41, 0x00 },
{ 0x42, 0x00 },
{ 0x43, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x32 },
{ 0x44, 0x50 },
{ 0x45, 0x00 },
{ 0x46, 0x00 },
{ 0x47, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x32 },
{ 0x4c, 0x02 },
{ 0x4d, 0x00 },
{ 0x4e, 0x00 },
{ 0x4f, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x32 },
{ 0x54, 0x00 },
{ 0x55, 0x88 },
{ 0x56, 0x40 },
{ 0x57, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x32 },
{ 0x58, 0x00 },
{ 0x59, 0x06 },
{ 0x5a, 0xd3 },
{ 0x5b, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x32 },
{ 0x60, 0x28 },
{ 0x61, 0x00 },
{ 0x62, 0x00 },
{ 0x63, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x33 },
{ 0x40, 0x00 },
{ 0x41, 0x00 },
{ 0x42, 0x00 },
{ 0x43, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x33 },
{ 0x64, 0x39 },
{ 0x65, 0x80 },
{ 0x66, 0x00 },
{ 0x67, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x07, 0x40 },
};

1) ASI Mode Control Register 0x14 is set to 0x6E . It seems this is configuring the device to be asi length of 24 bits and ASI Mode of LJF. Our file format is actually suppose to be mono PCM of 16 bits and 8 KHZ.

Hence I was thinking in order to meet my requirements, I need to change the settings or Register 0x14 to 10000b =0x10. Which changes the settings to 16 bit and mono PCM. IS THIS CORRECT

2)ASI Channel register 0x15 is set to 0x14 .Which seems to be set to LEFT Channel, I have decided to change this to 0x03 for monoPCM.

3) as you can see the clock settings are set for BCLK as input:(Not changed base on Pure COnsole)-

// Specify the clock (MCLK/BCLK)
{ 0x0f, 0x01 }, ///input blck and divider =1
// PLL P
{ 0x0f, 0x01 },
// PLL J
{ 0x10, 0x20 },
// PLL D - MSB 6 bits
{ 0x11, 0x00 },
// PLL D - LSB 8 bits
{ 0x12, 0x00 },
{ 0x00, 0x00 },
{ 0x7f, 0x00 },
{ 0x00, 0x00 },
Register PCM_RATE 0x36 is set to 0x33 finally and we changed it to 0x02 for 48khz.
all other registers were kept the same , based on pure console settings.

Based on above , i need to send it a wave file with the following properties :--

1) Sample rate 48khz

2) 16 bit pcm signed integer

Please can you confirm if the below file format is correct.

CLOCKS

Lastly based on Pure Generated output, is it correct for in terms of clocks:

As far as I have understood, the I2s Driver creates MCLK based on 48MHZ/Clock Divider ratio set in I2S Parameter's, however as our clock is above one mhz, we dont really need MCLK and can do with just BCLK. Currently when we checked the output freq of BCLK is around 1.55 mhz.

in the clock formula , I didn't understand how PLL Clock works. For instand we can choose if we want to use the source as BCLK or MCLK. In our case it is configured to use BCLK as the input and source for PLL_CLKIN.

Then according to data sheet you divide the PLL_CLKIN by the P value set in register 0x0f which is set to 1. But then I didnt understand how you use the J.D register values for the fractional multiplier? What does it mean by J.D( are you multiplying J and D) Sorry I am new to all this stuff.

thanks for your help

Hi Nadeem,

Given your description it seems BCLK = 1.536MHz and WCLK = 48kHz, is this correct? This is a more conventional use case than a mono 8kHz.
Since the ratio of BCLK to WCLK is 32, can you confirm you're adding 0's on the last 16-bit?
Your proposed register changes seem OK, you may try using LJF and left channel data as I think it should still work.

Just a couple things I noticed:

• In your initial description you mentioned 16bits and 8kHz, I assume this is a typo and should be 48kHz, correct?
• The audio file you uploaded seem like mono, 11.025kHz, 32-bit:
  • 

Best regards,
-Ivan Salazar
Applications Engineer