LM4550B: LM4550B CODEC

Amrutha k n

Part Number: LM4550B

Above is the interface between ADSP processor and LM4550B CODEC.

Issue: When CODEC is out of reset and receives the SYNC successfully, it is not generating a CODEC_READY bit 1 (Slot 0, Bit 15) although the frequencies at BITCLK & SYNC are expected.

Below is the waveform.

We are verifying our code with respect to AC97 link protocol CODEC STAC9753 by Tempo Semiconductors, and we are getting expected CODEC_READY bit 1 (Slot 0, Bit 15), below is the waveform with STAC9753

Note: LM4550B is a drop in replacement of STAC9753 with respect to registers and communication protocol.

Thank you

over 1 year ago

0 pdjuandi over 1 year ago

TI__Mastermind 29745 points

Hi,

I have responded to Kartik Vashisht in the email, we will use that instead so I will close this.

Regards.

0 Amrutha k n over 1 year ago

Prodigy 40 points

Hi,

Please omit the mail and consider this forum chain.

On the above matter I would like to add that; it is the CODEC who has to send the CODEC_READY = 1 in the SDI line (Slot 0, Bit 15) when it is out of RESET and we are not receiving this on the SDI line.

One observation is that the CODEC_READY is getting high for alternate SYNC (bits 14, 13, 12 & 11 in slot 0 are low)

Query: What is the default state of SDATA_IN pin?

Thanks

0 pdjuandi over 1 year ago in reply to Amrutha k n

TI__Mastermind 29745 points

I have to see the tag transaction from sync, bclk to get an idea of the not ready bit.

By default SDATIN_IN is in test mode this high impedance.

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LM4550B: LM4550B CODEC