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Hi,
Could you share customer schematic and PCB layout to me?
The Gain setting will be latched with power-up when SDZ pin is high. The end of the start-up cycle is when SDZ is high.
So could you monitor SDZ and Gain pin waveform together?
And if Gain pin is not stable, you can pull low SDZ pin to delay some time, then pull high SDZ pin when Gain pin is stable.
Hi Yanming,
There are IP issues, so no public schematics. Likely the problem is SD coming up with PVCC/AVCC. It would have been great if this was in the data sheet. I'll get our FAE to reach out to you by email.
Hi Gavin
I will follow email. Now I will close the E2E.
Thanks!
Regards,
Derek