PCM1820: Delay Between Applying Clock and Receiving Valid Samples in Slave Mode

This should be dependent on the decimation filter choosen. The group delay specification should give you the delay in FSYNC's

Given that the decimation filter is likely to be symmetrical, it should take twice the group delay for the filter to fully settle.  And that doesn't allow the chip any time to detect the FSYNC frequency, to determine which decimation filter to apply.

Tha application of FSYNC  and BCLK shall trigger the Automatic Clock Detection. This is based on counting to number of BCLKs in one FSYNC.This should take a minimum time of 1FSYNC to count BCLKS.

After this the Internal Clock setup and selection of decimation filter happens.