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TLV320ADC6140: No Digital Output

Jared Silbermann
Prodigy 125 points
Part Number: TLV320ADC6140
Other Parts Discussed in Thread: AM5729, AM5728

Hi, I am currently having some problems getting any output from the TLV320ADC6140 chip. Here is my configuration below:

tlv320adc6140: tlv320adc6140@4c {
compatible = "ti,tlv320adc6140";
#sound-dai-cells = <0>;
reg = <0x4c>;
ti,gpi-config = <0 0 0 0>; 
ti,gpio-config = <2 2>; 
ti,gpo-config-1 = <0 0>; 
ti,gpo-config-2 = <0 0>; 
ti,gpo-config-3 = <0 0>; 
ti,gpo-config-4 = <0 0>;
reset-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; 
status = "okay";
};

I am using mcasp in master mode to provide the BCLK and FSYNC which I have confirmed abide by the following formula:
BLCK >= FSYNC * word_length * #_channels

ALSA is correctly picking up the sound card created using simple-sound-card:
[ 1.602680] asoc-simple-card sound-adc: tlv320adcx140-codec.2-004c <-> 48460000.mcasp mapping ok

I2C communication with the chip works fine.

As a test, I am currently leaving the SDOUT pin unconnected to my AM5729 board to purely see serial output from the chip and not worry about anything else. However, there is no signal on the line when an arecord is run despite the appropriate clocks starting and at the correct frequency. My input signals are going over line in. I have also run alsamixer and confirmed that everything is unmuted with the input mux set to LINE_IN. 

Any assistance would be greatly appreciated,

Jared

  • 0
    TI__Genius 16130 points

    Hi Jared,

    To help me troubleshoot, can you provide your register dump of ADC6140?

    Regards,

  • 0 in reply to Daveon Douglas
    Prodigy 125 points

    Here is an I2C dump. Let me know if you need any other information

    i2cdump -y -a -f 2 0x4c

  • 0 in reply to Jared Silbermann
    TI__Mastermind 31075 points

    Hi Jared,

    Register 0x76 is reporting that the ADC channels are powered down. Register 0x77 is also reporting that the device is in active mode with all ADC channels powered down. However 0x75 shows you're trying to power on the ADC channels. Are all of your power supplies correct?

    Best regards,
    Jeff McPherson

  • 0 in reply to Jeff McPherson
    Prodigy 125 points

    Hi,
    My power supplies are 3.3V going to AVDD to IOVDD and AREG is internally generated. Just an update, I noticed there was a clock error interrupt triggering (most likely due to the mcasp sending a pulse at start-up). However, on running an arecord this interrupt is cleared and 0x73 reads the correct value of f0 indicating the 4 input analog channels are enabled. Unfortunately, this does not lead to any change in the register 0x75-0x77. I am attaching an updated i2cdump below taken whilst an arecord is running:


  • 0 in reply to Jared Silbermann
    TI__Genius 16130 points

    Hi Jared,

    Your registers seem okay, can you confirm what you're BCLK and FSYNC is running at?

    Also, when you're writing to the device, please see the design sequence outlined in section 9.2.1.2. of the datasheet to ensure proper operation. There is an example script following this section to help.

    Regards,

  • 0 in reply to Daveon Douglas
    Prodigy 125 points

    arecord -D hw:1,0 -c2 -f S16_LE -r 48000 test.wav

    BLCK: 1.5MHz
    FSYNC: 39.062 kHz

  • 0 in reply to Jared Silbermann
    TI__Genius 16130 points

    Hi Jared,

    The BLCK and FSYNC frequencies your providing may be creating some form of an ASI bus clock error. Whether it be an invalid BCLK:FSYNC ratio or invalid FSYNC all together. This will shut down the record channel instantly.

    Please see section 8.3.2 of the datasheet for supported FSYNC frequencies (must be a multiple of 44.1kHz or 48kHz) and BCLK frequencies.

    Best Regards,

  • 0 in reply to Daveon Douglas
    Prodigy 125 points

    Hi Daveon,

    I can see the clock frequency issue and am in the process of resolving it. Just wondering if you can point me in the right direction of controlling the divisor from the BLCK to FSYNC frequency. The McASP Design Guide makes reference to Rx FSG in figure 2 that sits between BCLK and FSYNC. However, I cannot seem to find any reference to this in the datasheet, nor any control over the divisor down to FSYNC within the register outline. I can see with my given sys clk frequency at 2.4576 Mhz I will need a 512 division factor from sysclk down to achieve an fsync of 48 khz and that hopefully should resolve my issues.

    Regards

  • 0 in reply to Jared Silbermann
    TI__Genius 16130 points

    Hi Jared,

    Just to note, you can provide the necessary BCLK and FSYNC frequencies as outlined in the table of section 8.3.2 or you can configure the device in master mode providing solely an MCLK to generate the lower jitter ASI clocks (BLCK & FYSNC). These are two common methods to achieving the correct clocks. More information about the latter can be found here: Configuring and Operating TLV320ADCx140 as Audio Bus Master

    In regards to McASP programming of AM5728, I apologize as I'm not very familiar with that device. Please post a question to Sitara MCU experts, they will be able to assist you.

    Kind regards,