TAS2770: TAS2770

Hi Divya,

You may find the reference driver in TI git: tas2770sw-android/tas2770sw-android - Android software for Texas Instruments TAS2770. (ti.com)

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan

Thanks for the update 

All the registers are in the default reset state when we checked the i2cdump and also at this stage we are not able to hear the audio 

So can you please let us know the list of registers that need to be configured for the speaker playback

Hi Divya,

That's correct, default reset values set the device in software shutdown. You have to at least enable the device by setting page 0 register 2 bits 1:0 to "00", this takes the device into Active mode.
You may use PPC3 software to configure any required features, and then use the "Export I2C" tool to generate the configuration files. The header (.h) files should be used along with the driver to define the register settings.

Best regards,
-Ivan Salazar
Applications Engineer

Hi 

Hi 

Currently driver which you have shared is not compatible with our kernel (We are facing crash issues)

So can you please share us the driver for the kernel version 5.4

Hi Divya,

I'll check on availability of different version of the driver with our software specialists. Please allow a couple of days to get some feedback.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Guy

I don't think porting the old Linux driver on 5.4 will cause crash. Kindly share the log with us.

One more thing, if the old tas2770 linux driver is uncomfortable to you, you can use following code for tas2770, but it support kernel 5.10. 

What your extra work is to create a json file to set the registers and convert it to a bin file and compile it into your device

Add regbin json file for tas2110 - lpaa-android-drivers/tasdevice-linux-driver - Unnamed repository; edit this file 'description' to name the repository.

the guideline is doc - lpaa-android-drivers/tasdevice-linux-driver - Unnamed repository; edit this file 'description' to name the repository.

The tool is tool - lpaa-android-drivers/pcmdevice-linux-driver - Unnamed repository; edit this file 'description' to name the repository.

Good luck

Shenghao

Hi 

By default SW register settings is been written as 0x02 in 0x0E which is in shutdown state.

We tried to write using i2c as 0x00 but still when we read it back it shows 0x02 which is again SW shutdown

Is there anything else we are missing here?

Please help here

So, which code you are using now, tas2770 or tasdevice?

For tasdevice, you must put bin file into the /lib/firmware. the json file is in json - lpaa-android-drivers/tasdevice-linux-driver - Unnamed repository; edit this file 'description' to name the repository.

Hi

We are using tas2770.

Can you give 48khz sample rate i2c registers settings

On addition to that what is the bitclock and mclk which need to be provided for driving audio through this codec?

Whether any registers are there to adjust bitclock higher than the  required value

Hi 

tas2770 is a slave chip, can't product the clk. It depends on master clk. Our chip can auto-detect sample rate. Kindly measure the i2s bitclk and WS clk with scope. During playback, the both clks must be on first.

BR

Shenghao Ding

Hi Ding 

We are getting 1.5MHz as Bit clock and Mclk as 6.144MHz from our processor.

Will this cause as software shutdown?

Also can please tell us the all registers which we need to write and to get away from Software shutdown? 

For tas2770, the bit clk and ws clk is the mandatory. bit clk should be 1.536 MHz and ws clk is 48kHz.

Kindly check the ws clk and the duty cycle of the clk, it must be 50%. I recommend you to use tasdevice driver. tas2770 is a very old one.

What's more all the regsiter settings are in the bin file in tasdevice, it will be easy for the developer to change the register settings

Hi Ding 

Yes we have started porting to tasdevice.

Meanwhile Can please say the i2c registers which we need to write, because it is in software shutdown now.
We need to make this in active mode.

Can you please help here.

Hi Guy

The most probable root cause is the clk issue. Kindly use scope to measure check the ws clk and the duty cycle of the clk, it must be 50%. Don't forget to upload the waveforms.

As to tasdevice, do not forget to add bin file into the system.

Hi 

We are sharing here the wave form snapshot . Here we are getting the bit clock as 1.5MHz and WS clock as 48kHz and duty cycle is also 50% but we are not able to hear the audio

t

We are suspecting some I2C register only so we are sharing the register dump as well as the registers configuration that we made

Please help here

According to b0p0r0x24=0x04, which means clk issue
In b0p0r0xa, why set bit5 to 44.1kHz? Since the samperate is 48kHz?
In b0p0r0x77, still shows clk wrong.
Kindly set b0p0r0x3c as 0xc
set b0p0r0xc as 0x30
Do not set b0p0r0xa, default value is good for your clk.

One more thing, have the tasdevice driver worked? you can set the register setting into the regbin file instead of i2cset, it will make your debug more efficiency.

Hi

We have tried the same but at that case its going to SW shutdown case

dump the registers, thanks

Hi Ding 

From my side b0p0r0x77 and  b0p0r0x24 is OK, I will ask hardware guy to support this.

Hi

I am sharing my current i2c register dump and register configuration 

Hi Divya,

Is my understanding correct that you're only writing this reduced initialization script of 7 commands? Should I assume you can't use a configuration file generated from PPC3?

For mono applications, the host must still transmit at least 2 channels, and the amplifier will only use the data of one of these only, either left or right or a mix of both.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan 

Yes we cant use PPC3 configuration generated file.
But we can use i2cset and i2cget commands 

Is it possible to give the header file which is working for your side.

Hi Divya,

I can share a cfg file, you would have to parse it into i2cset commands.
I'll upload the cfg by the end of the day tomorrow.

Best regards,
-Ivan Salazar
Applications Engineer

Divya Barathi said:

i2cset -y -f 1 0x41 0x00 0x00
i2cset -y -f 1 0x41 0x00 0x00
i2cset -y -f 1 0x41 0x00 0x01
sleep 0.01

Do you want to set page 01 or want to reset chip, reset chip should be

i2cset -y -f 1 0x41 0x00 0x00
i2cset -y -f 1 0x41 0x7f 0x00

i2cset -y -f 1 0x41 0x01 0x1

sleep 0.01

Hi Ding 

After add reset also 
it is still in SW shutdown only.

Expecting your cfg file. 

Thanks
Divya 

Hi Divya,

Attached is a script for default settings on TAS2770.
Please parse it into i2cset commands for test and let us know if it works better.

Best regards,
-Ivan Salazar
Applications Engineer

TAS2770_initConfig.cfg

Hi Ivan 

Thanks for sharing the config file. 

I can see only 37 registers 
Whether these registers are enough to play through speaker?

If anything is being missed can you please send the same also.
Our expectation is all registers for tas2770 which we will be used for playing speaker.

Shenghao Ding said:

i2cset -y -f 1 0x41 0x00 0x00
i2cset -y -f 1 0x41 0x00 0x00
i2cset -y -f 1 0x41 0x00 0x01
sleep 0.01

i2cset -y -f 1 0x41 0x00 0x00
i2cset -y -f 1 0x41 0x00 0x00

these two lines are same, it is wrong

Hi Ding 

Yes I accept, I am expecting all the necessary registers which I have to write for playing the speaker. 

Hi Team 

Expecting the reply from your side. 
Please help here. 

HI Divya,

The attached cfg was generated using PPC3, it has all required register writes.

Please parse it into i2cset commands for test and let us know if it works better.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan 

Is there any new attachement which you have sent?
or you are referring to the old one?

Hi Ivan and Ding 

One more previously you confirmed Bitclock is 1.5MHz and WS clock is 48Khz 


but in data sheet they have mentioned like 

<SBCLK Input Frequency I2S/TDM Operation 2.54 27.1 MHz>

Because we are getting BCLK as 1.5MHZ 

please confirm this 

HI Divya,

If you raise the bitclk to 3.072, 32-bit, 48kHz, does it work?

Hi Ding 

We didnt try that 

Can you please attach a sample default audio file with the below settings 
1.5Mhz bitclock and 48KHz as sampling rate and Mono Channel 

One more question does tas2770 support below formats <Signed 16 bit Little Endian, Rate 48000 Hz, Mono> 

If yes means can you please send the i2c configurations for this 
Because we are always getting TDM clock and 0x77 register to 0x7f value.

Please help here.

I will ask Ivan to check whether it support 1.536MHz. I realize that no 1.536MHz was mentioned in datasheet

Hi Divya,

I'll double check the 1.536MHz use case on the EVM and get further feedback within the next couple of days.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan 
Any update on this?

Hi Divya,

I tested the EVM with 1.536MHz as SBCLK frequency, it works OK with the same script I shared before.
The script is attached again (I'm just adding few last commands to set the device into Active mode)

5635.TAS2770_initConfig.cfg

Here's the Host format configuration for reference:

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan 

Thanks for sharing Config file and format configuration. From this we confirmed that we are not seeing TDM clock and 0x77 register is setting properly. 


But we are seeing 0x26 register setting to 03 which last two bits are setting high. Means Interrupt due to LDO 5 V PG flag (read to clear) and Interrupt due to LDO 5 V OL (read to clear) sets high after reboot. 

Explaining more clearly 

When we boot the device and see the i2cdump we are seeing 0x26 as 03 by default. Then if we try to play audio file, we are getting 5b , which means 11000011,  Interrupt due to clock halt flag (read to clear), Interrupt due to DMA Request to DSP lost flag (read to clear), Interrupt due to LDO 5 V PG flag (read to clear), Interrupt due to LDO 5 V OL (read to clear). are setting high


Can you please let us know, which may be the root cause for this bits getting high? In datasheet also we are not able to identify the root cause.

Hi Divya,

Do you have a schematic and layout we can review? Please check DREG pin with oscilloscope when you power up the device. It seems an internal regulator is being overloaded.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan 

Yes we will be sharing the schematic and layout shortly.

Meantime we have  probed the DREG rail. Below is the voltage we observed. 

Also, while probing the ripple, we have the below observation.

Please help here

Hi Divya,

Is this capture after you sent the command to take the device into active mode in register 2?

I'd like to see if there's any bump or dip when the device tries to become active.

Best regards,
-Ivan Salazar
Applications Engineer

Hi Ivan 

What is the expected voltage in DREG. We are seeing 1V.

Hi Ivan 

We are able to drive the speaker through EVK. 

But small query, Once we start playing audio, we are missing few initial data, because once we give play request and made if we made the register 0x02 as  0x0c only audio is playing. Is this expected.

Can we able to queue the data?

Hi Divya,

The observed DREG voltage is OK:

You can set the device into Active mode by writing into register 0x02 at any time once the BCLK and FSYNC clocks are running, DIN data can be generated after that.

Best regards,
-Ivan Salazar
Applications Engineer