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TAS5756M: I2C data hold timing

Koji Yajima
Prodigy 10 points
Part Number: TAS5756M

Hi.

In the TAS5756M datasheet, it mentions a I2C data hold time of Min. 0ns and Max. 900ns.

Does this mean that the SDA signal MUST change within 0 to 900ns after the falling edge of SCL?

I understand that, according to the I2C specification, it's acceptable for data changes to occur beyond 900ns,

but I'd like to confirm this. Can anyone provide clarification?

  • 0
    Prodigy 10 points

    PS

    I remembered that the SDA signal was bidirectional.

    Could it be that the Min. of data hold is a provision for the device input timing of SDA

    and Max. is a provision for the device output timing?

    In any case, I think the description in the datasheet is ambiguous.

  • +1 in reply to Koji Yajima
    TI__Mastermind 49900 points

    Hi Koji

      This 900ns requirement only works for extremely using conditions, and needn't to take care for most of the time. The key parameter is actually the Data Setup Time, minimum 100ns must be guaranteed. To guarantee this value, if we consider all the extreme using condition. The smallest Low period of SCLK is defined as 1300ns, and if the rising time is also the lowest, would take 300ns, it's only 1000ns left. We need at least 100ns for Data Setup time, so only 900ns could left for the Data Hold Time. That's where this value comes from.

       But as I said, for most of the time, you needn't take care of this value. Only make sure the 100ns Data Setup Time could be guaranteed would be fine.