PCM6020-Q1: PCM6020-Q1 analysis speaker

Can you please elaborate on the functionality needed from the ADC?

We need get ADC feedback data then compare original data confirm the data whether or not change by SOC 

This should work

Whether or not have some different with normal design of input portion.What portion need been highlight before design

The signal can be C Coupled to ADC chip as shoen

C0 suggest value and R0 value ?could you give us some suggest 

Can you please send me the maximum signal level and minimum signal frerquency coming from the DAC?

DAC Max signal level is 15W (about voltage is 7.75V),min signal frequency is 20HZ 

Is the signal 7.75Vpp?

Yes,this is base on speaker spec estimated but it’s not final  result due to current speaker vendor no fix 

The signal of 7.75Vpp will couple through the capacitor and shall ride on the MicBias Level. 7.75vPP implies a Vp of 3.875V..Therefor a micBias of Greater then 4V can be used.Please set 5V.

Use Ro=4k7 and  C>1/2*3.14*20*4700  =1.6uf can be used. I suggest to use C=4.7U  

OK，got it.TKS 

Hypothesis the worst case Vpp  is 24V (12V power level ).the MicBias level set 15V，RC follow the format  it’s ok? the speaker vendor no fix,maybe spec will been change.

The maximum pin voltage is 18v . If the MicBias is coming from an outside source is 15v then i would suggest placing a series resistor in series with the coupling capacitor.. This shall form a voltage divider with the 4K7.

24*4K7/(R+4K7)=6.v

R is approx 15k

This would limit the pin voltage to 6vpp so that the pin goes to 15+(6/2) or 18v