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DSD1793: Setting/Function of OS bits in DSD Mode

Part Number: DSD1793

Page 42 of the DSD1793 datasheet refers to the OS bits, in DSD mode, selecting the operating rate of the analog FIR.

My question is, under what conditions would a selection other than the default be chosen?

In my experiments, any setting other than the default results in a very high noise floor and... generally what appears to be, not working correctly.

It isn't clear to me the role and application of this FIR filter, is there an application document or something describing its role in the circuit?

  • Hello Fritz, 

    The OS bits change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation allows the use of only a single type (cutoff frequency) of post low-pass filter. 

    I could not find any application note regarding this part but you should be able to find many general informative documents  regarding FIR .

    Regards,

    Arash

  • The text clip you provided from page 30 of the datasheet does not apply to DSD mode, according to page 42 of the datasheet: "The OS bits in the DSD mode select the operating rate of the analog FIR. The OS bits must be set before setting the DSD bit to 1."

    My question relates to DSD mode. Under what conditions would one set these bits to a configuration other than the default?

  • Ok, I understood your question regarding the DSD operation.

    My understanding is that  these bits sets the Standard , double or quadruple speed versions. Where the default setting is the full speed -user can go to 1/2 or 1/4 speed as well. Please refer to the last paragraph of the following . Hopefully it answer your question.  

    DSD uses a single bit of information, and all this information tells us is whether the current sample of the analog waveform is higher or lower than in the previous one. Compared with the over 65,000 different values 16-bit PCM has, the two values (0 if the new sample if the signal is lower or 1 if it’s higher) of DSD appear mighty limiting.

    That resolution shortfall is made up by the very high sampling rate of over 2.8 million times a second – that’s 64 times the speed of CD. Standard DSD is sometimes called DSD64 for this reason, with double and quadruple speed versions called DSD128 and DSD256 respectively. 

    • DSD 64     : DSD 2.8 MHz   =  2 822 400 Hz = 44100 Hz x 64 times;
    • DSD 128   : DSD 5.6 MHz   =  5 644 800 Hz = 44100 Hz x 128 times;
    • DSD 256   : DSD 11.2 MHz = 11 289 600 Hz = 44100 Hz x 256 times;