PCM6020-Q1: Multiple PCM6xx0 devices with hared TDM and I2C Bus about register issue

Hi Lawrence,

Lawrence He said:

Q1: Setting ADC of Word(Slot) Length, the ADC can read TDM slot

You configure the ASI format to the audio input data. You can configure the ASI format to a wordlength of 16bits but if the audio data is 32-bits long, it will truncate. Vice versa, the device will append the data with 0's.

Lawrence He said:

2: about setting ADC of Channel Slot Assignment ,so the ADC can appoint each one analog channel data to TDM slot

Correct, its easier to visualize through the PPC3 GUI, I suggest requesting/downloading on ti.com/mysecuresoftware to help with this.

Regards,

Hello Daveon Douglas,

I have two questions. We have only ADC and we want to configure to TDM8 with sample rate 48KHz, BCLK 24MHz and FSYNC 48KHz.

Firstly, I would like to understand how to configure the TDM slot number. I couldn't find any register in the datasheet to directly set the slot number. What I did find is that the ADC depends on the Host Processor to provide FSYNC and BCLK, and we can configure the Word (Slot) Length.

Secondly, I am curious about the process of assigning data to TDM slots. As per the datasheet, it mentions that configuring the ADC's Channel Slot Assignment allows the ADC to specify which TDM Slot should be used to place data from each analog input channel. Is my understanding accurate?

Appreciate your assistance with these questions.

HSIN TANG HUANG said:

Firstly, I would like to understand how to configure the TDM slot number. I couldn't find any register in the datasheet to directly set the slot number.

This is configured in page 0, 0xB and 0xC.

HSIN TANG HUANG said:

Assignment allows the ADC to specify which TDM Slot should be used to place data from each analog input channel. Is my understanding accurate?

Correct, this is useful in the case where you're sharing a TDM bus across multiple devices. On device 1, you can have ch1 & 2 configured to slot 0 and 1. On device 2, ch1 & 2 can occupy slot 2 and 3 and so on. The EVM and GUI is designed to support our our 6 CH device but all of our PCM6xxx0-Q1 devices are software compatible, so this is why you have a slot count up to 64 in the register map.

Example of the PCM6240 (4 Ch) GUI configuration below.

Regards,

Hello Daveon Douglas,

This is configured in page 0, 0xB and 0xC

>>> My apologies for not providing a clear explanation. Is my understanding correct that register 0xB is used to assign Channel 1 data to a specific TDM slot? If so, what I would like to know is how to configure the total TDM slots, such as TDM 8, 16, or 32. Specifically, how do I configure it for TDM 8 format, and how do I configure it for TDM 16 format?

Hi HSIN,

This is noted in section 3 of the application note you linked earlier. The device can support up to 8 channel slots per device (TDM8) and can be configured so through the clocking provided. The BCLK must be ≥ (# channels/device) × (# devices) × (sample rate) × (word length) but can't exceed the max BCLK of 25Mhz. You can provide a BCLK that supports up to 8 channels and if you're using only one PCM6020 device (i.e 2 channels) the 6 remaining channel slots will be 0's. If you're using four PCM6020's, then you can write to 0xB and 0xC to configure the slot for each device to fill the entire TDM8 data line. 

One device alone doesn't support TDM16. But with multiple devices, for example, provide a BCLK = (8 CH) x (2 devices) x (48Khz) x (32bit WL) =24.576MHz to cascade two data lines on 1 TDM bus to achieve TDM16.

Regards,

Thank you for your response. I'd like to confirm that to configure the TDM 8 format with a sample rate of 48 KHz and a word length of 32 bits on one ADC device, I need to:

1. Set the protocol format to TDM mode.
2. Set the word length to 32.

3. Provide FSYNC at 48 KHz and BCLK at 12 MHz to the ADC.

This configuration will allow the ADC to recognize it as a TDM 8 format since (12 MHz, BCLK) = (8, TDM 8) × (48 KHz, Sample Rate, FSYNC) × (32, Word Length).

Is my understanding correct?