TLV320ADC3140: Usage in Slave Mode

Hi Ryu,

Your source clock, BCLK, in this case should be = 4 channels x Fs (48kHz for example)  x world length (ex. 32 bit depth )  >= 6.144Mhz. The PLL only supports sampling frequencies that are multiples or submultiple of 44.1kHz or 48kHz. See section 8.3.2 of the datasheet for the necessary clocks, the device has auto clock detection so there no need to manually configure the PLL.

MST_CFG1 is a register that is used when the device is configured for master mode in MST_CFG0. When the device is in slave mode (default), the device will not reference that register for instructions.

Regards,

Hi Daveon,

Thanks for the reply.
I understand.
If I use it in master mode, does that mean I can't use the sampling frequency I want to use?
If I want to use it at the frequency I want to use, should I use some other device?
If so, I would like to know the device as well.

Sincerely,
Ryu.

Hi Ryu,

The image below shoes the supported MCLK input frequencies (provided by user) and sample rates. This is explained further here: Configuring and Operating TLV320ADCx140 as Audio Bus Master

So the better question is, what is the desired sampling rate and at what input MCLK frequency?

Regards,

Hi Daveon,

If I input MCLK, BCLK and FSYNC all by myself without PLL, is it correct that there is no limit on MCLK?
Can I use unsupported frequencies (MCLK=13.1072MHz, BCLK=MCLK/2=6.5536MHz, FSYNC=MCLK/256=51.2kHz) without using PLL when using in slave mode?

Sincerely,
Ryu.

Hi Ryu,

Unfortunately, whether in master or slave mode, the TLV320ADCx140/PCMx140-Q1 device family only supports two sets of sample rates. One set of sample rates cover the nine submultiples and multiples of 48 kHz, from 8 kHz to 768 kHz. The other set of sample rates cover the sample rates from 7.35 kHz to 705.6 kHz, which are submultiples and multiples of 44.1 kHz..

Regards,

Hi Daveon,

Thanks for the reply.
Is that the same without PLL?
I thought only a limited sample rate could be used due to PLL limitations.
So which ADC should I use if I want to operate at the frequency I just wrote with similar specs?

Sincerely,
Ryu.

Hi Ryu,

With disabling the PLL, this may be possible. I will confirm on the EVM early next week and update thread accordingly.

Kind regards,

Hi Daveon,

Thanks for the reply.
Can you give me the exported config file so I can try it with that configuration?

Sincerely,
Ryu.

Here is a preset configuration that was used during validation. At 51.2kHz Fs, If you're using the EVM or read register xxxx the device will state that the clocks are 48kHz despite the incoming 51.2kHz. For example if you delivered 10khz Fs the device would read the closest multiple of 48/44.1 so the device would read 8kHz

# CHECKSUM 0
# Generated by ADCx140EVM-SW v3.0.5
# TLV320ADC3140 device configuration
# -----------------------------------------------------------------------------
# Reset
# -----------------------------------------------------------------------------
# Select Page 0
w 98 00 00
# Reset Device
w 98 01 01
# 1mS Delay
# -----------------------------------------------------------------------------
# Begin Device Memory
# -----------------------------------------------------------------------------
# Page 0 (0x00) Dump
# Select Page 0
w 98 00 00
# Wake up and enable AREG
w 98 02 81
# Clock Error Disable/Enable
w 98 04 40
# Channel 1 configuration
w 98 3c 80
# Channel 2 configuration
w 98 41 80
# Channel 3 configuration
w 98 46 80
# Channel 4 configuration
w 98 4b 80
#DSP configuration
w 98 6c 48
# Channel Input/Output Configuration
w 98 74 f0
w 98 1e 82
# M divider Enabled with Divider Value
w 98 1f c0

Regards,