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TLV320AIC3106: Output Common-Mode adjustment not working

Guillermo Corrales
Intellectual 295 points
Part Number: TLV320AIC3106

Hello all,

We are using a TLV320AIC3106 in an scenario where we adjust the levels of a microphone signal received in LINE1LP pin (in signle-ended mode) and we output it through LEFT_LOP.

We have recently realized the signals outputed by LEFT_LOP are saturating at slightly less than 2.7V Vpk-pk. After reviewing the datasheet we have detected a setting we did not noticed before: the "Analog Output Common-Mode Adjustment". After navigating through the datasheet we ended discovering "Page 0 / Register 40: High Power Output Stage Control Register" and after that we modify the bits D7-D6 from 00 to 10 since we are powering the IC with 3V3 for IOVDD / DRVDD and 1V8 for DVDD. 

We checked again LEFT_LOP output voltage saturation level and... unfortunately nothing changed, output still saturating at slightly less than 2.7V Vpk-pk so it seems we are missing something.

Right now we have the following questions:

  1. Output Common-Mode adjustment works as we expect? I mean:
    • It affects the behaviour of LEFT_LOP output both in single-ended and differential mode
    • If D7-D6 = 00, then  LEFT_LOP output signal will saturate at 2V7.
    • If D7-D6 = 10, then LEFT_LOP output signal will saturate at 3V3.
    • "Page 0 / Register 40: High Power Output Stage Control Register" is the right register to modify not only HPLOUT but also LEFT_LOP outputs Output Common-Mode adjustment. I ask this because the name of the register is somewhat misleading.
  2. Can "Page 0 / Register 42: Output Driver Pop Reduction Register" bit D1 be related with this topic?
  3. If with our current configuration (D7-D6 = 00) output signal saturates at aroung 2.4V instead of 2.7V (Vpk-pk). Could this mean that we are limiting the output voltage in a different way than with Analog Output Common-Mode Adjustment? If the answer is yes then:
    • If we are unintentionally limiting this output voltage range to let say 2.4V, Would D7-D6 bits value affect? or it wouldn't matter to have it configured to 2V7 or 3V3 since the signal is limited earlier to 2V4?
    • What registers could also affect the output voltage range?

Do you have any guidance of what can we doing wrong? Please not input signal is around 2.3V (Vpk-pk) and is NOT saturated.

Thank you very much in advance!

Best regards,

  • 0
    TI__Mastermind 29745 points

    Hi,

    You can read more of this output common mode in section 10.3.3.3.6 of the datasheet and this table provide the recommended setting based on the supply.

    1. The maximum output swing for single-ended is 0.707Vrms or 2Vpp for either LO or HP as shown in the datasheet. 2.7Vpp is beyond this so it will clip.

    2. No, see 1 above.

    3. See above. For single ended the output level only up 2Vpp and 4Vpp for differential. 

    Regards.

  • 0 in reply to pdjuandi
    Intellectual 295 points

    Hi Pdjuandi,

    Thank you very much for your response.

    I already read the section you mention before asking my questions in the forum. The problem is I'm not 100% sure of understand the information it contains:

    • The section mentions not only output common-mode voltage but also output range. I understood the Analog Output Common-Mode Adjustment no only affected common-mode voltage but also output range. Is my assumption right?
    • The full-scale output voltage value the datasheet provide is a typical value refered to a CM mode = 1V35, not a maximun value. If 2Vpp is the real maximun value then how is it possible I'm seeing 2.4 Vpp?

  • 0 in reply to Guillermo Corrales
    TI__Mastermind 29745 points

    Hi,

    Yes, the range of output voltage and CM are related. That's why table 10-5 was provided.

    The typical value is what the device is designed to meet. Beyond that, it's not spec'd to meet, and clipping can happen if drive beyond that.

    Regards.

  • 0 in reply to pdjuandi
    Intellectual 295 points

    Hi,

    I understand what you say about typical value, but since it is refered to CM configuration, I understand typical value is a function of CM configuration, so if I increase CM from 1V35 to 1V65 typical vaue may change. Is my assumption right?

    Apart of that, I have understood from your previous response you have confirmed output voltage is related to CM configuration. Am I right? If the answer is yes, then it do not make too much sense to be able to change output voltage range while clipping threshold is fixed to ~2Vpp.

    Can you please clarify me this two points?

    Thank you very much in advance!

  • 0 in reply to Guillermo Corrales
    TI__Mastermind 29745 points

    No, the typical is the same as you change the CM. 1.35V is used as it covers the supply range from 2.7V-3.6V, for 1.8V CM only 3.6V AVDD is recommended.

    See the highlighted for the different CM option, the output level is still the typical for any of the CM.

    The output voltage is 0.707Vrms single ended, so if you connect LINE1L input directly to LO the maximum input level is the same as the LINEOUT SE level so it will not clip and so is with DAC input. See table for the respective input for ADC and DAC (0 dBFS = 0.707Vrms).

    I think you configured the register incorrectly for analog bypass mode from LINE1LP to LEFT_LOP.

    You will need only register 86 and 108 for this path.

    You don't need to set the CM in register 40 for the analog bypass path, it will be based on the AVDD supply.

    Hope this help.

  • 0 in reply to pdjuandi
    Intellectual 295 points

    Hi Pdjuandi,

    Thank you very much for your response.

    I think I'm finally starting to get your point, I only need you to clarify me one last thing:

    • Can you please explain me what exactly does CM adjustment? I mean, what change should I expect to see at the output when I change this values?

    In any case, we are not working in direct analog bypass mode. The current audio path is: analog input -> TLV320AIC3106 -> Jacinto6+ -> TLV320AIC3106 again -> analog output

    Regards!

  • 0 in reply to Guillermo Corrales
    TI__Mastermind 29745 points

    It's basically just setting the output CM to half of its supply; the output full range itself is still 0.707Vrms (2Vpp).

    This setting allows user the flexibility to take the output and feed into device which requires different supply for example.

    From the codec side, it's also setting a balanced biasing for the push-pull transistors.

    So as long as your output does not exceed the datasheet 0.707Vrm, the signal will not clip.