TLV320ADC3140: Different Fs from 44.1kHz or 48kHz.

Shunsuke Yamamoto

Part Number: TLV320ADC3140
Other Parts Discussed in Thread: TLV320ADC3100

Hi team,

Is TLV320ADC3140 possible to work with Fs=51.2kHz, 25.6kHz or 12.8kHz in slave mode operation? My customer tries to input all clock signals(FSYNC and BCLK) from external MCU to TLV320ADC3140 wokring in slave mode. Based on the attached pdf, these Fs are not supported with both PLL enabled case and PLL disabled case. I would like to confirm.

sbaa379.pdf

Best regards,

Shunsuke Yamamoto

over 1 year ago

0 Jeff McPherson over 1 year ago

TI__Mastermind 42295 points

Hi Yamamoto-san,

This device only supports the sampling frequencies listed in Table 6 and 7 of the datasheet (multiples of 48k and 44.1k).

To support these non-standard clock rates you'll need an ADC that has a fully programmable PLL like the TLV320ADC3100.

Best regards,
Jeff McPherson

0 Shunsuke Yamamoto over 1 year ago in reply to Jeff McPherson

TI__Expert 6971 points

Hi Jeff,

Could you please also check if it is not really possible by TLV320ADC3140EVM?
Best regards,

Shunsuke Yamamoto

0 Jeff McPherson over 1 year ago in reply to Shunsuke Yamamoto

TI__Mastermind 42295 points

Hi Yamamoto-san,

Sure, I will experiment on an EVM today at let you know if it's possible or not.

Best regards,
Jeff McPherson

0 Jeff McPherson over 1 year ago in reply to Jeff McPherson

TI__Mastermind 42295 points

Hi Yamamoto-san,

I tested on an EVM and found that with PLL set to auto-configure, Fs 51.2kHz and 25.6kHz works. 12.8kHz does not work.

Best regards,

0 Shunsuke Yamamoto over 1 year ago in reply to Jeff McPherson

TI__Expert 6971 points

Hi Jeff-san,

Thank you so much for the evaluation! It is good to know that TLV320ADC3140 works with Fs51.2kHz and Fs25.6kHz even though we haven't stated it on the datasheet. I would like to introduce how to configure your setting with Fs51.2kHz and Fs25.6kHz to the customer. In my understanding, we can copy your setting by following the instruction below on sbaa379.pdf. Could you please teach me?

Best regards,

Shunsuke Yamamoto

+1 Jeff McPherson over 1 year ago in reply to Shunsuke Yamamoto

TI__Mastermind 42295 points

Hi Yamamoto-san,

The app note you're referring to is not very helpful with learning device configurations. The datasheet is better for this. There is an application section that contains an example configuration script (9.2.1.2.1). But you are correct, all you need to do is power on the PLL when you power on the ADC channels. By default the PLL is set to auto configure itself after receiving MCLK, FSYNC, and BCLK. This will configure the PLL to the proper dividers to support 51.2k and 25.6k sampling.

Best regards,
Jeff McPherson

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TLV320ADC3140: Different Fs from 44.1kHz or 48kHz.